The &ects of various cache coherence strategies are analyzedfor a multiported shared-memory multiprocessor. Analytical models for Concurrent-Read-Exclusive-Write access (CREW) ana' Concurrent-Read-Concurrent-Write access (CRCW) are developed including shared-notcacheable, snooping-bus, snooping-bus with cache-tocache transfers, and directory protocols. The performance of each protocol is shown as the hit rate, min-memory-tocache-memory cycle-time ratio, fraction of shared data, read percentage, and number of partitions are varied. Overall, results indicate that a snooping-bus with cacheto-cache transfer scheme provides consistently fast access times over a wide range of execution parameters. However, nearly equivalent pe@ormance can be obtained with simpler directory-based schemes. The implications of these results on increasing port complexity and memory usage are discussed.