Two alpha-particle counting systems for the measurement of large-area sources have been developed at the National Bureau of Standards. The systems and their characteristics are described. One system uses an internal-source proportional counter and the other measures sources external to the counting volume through a thin aluminized mylar window. The "internal" system is used to measure sources in the lower activity ranges. These calibrated sources are then used to establish the efficiency of the "external" counter used to measure the higher-activity sources.

Abstract. Luo converter is one amid the developed DC-DC converters offering higher voltage gain. Soft-switching techniques, like zero-voltage switching (ZVS), repress switching losses, and hence the system efficiency and the life of the power semiconductor switches are improved. Incorporation of soft switching in fixed-frequency operation of the Luo converters may persuade them in the regulated power supply applications. The existing variable switching frequency solution suffers from a number of problems viz. complexity in filter designing, more electromagnetic interference (EMI), etc. This paper proposes a positive output elementary Luo converter (POELC) involving ZVS with the wherewithal of working in fixed frequency. A comprehensive discussion on the proposed circuit topology is detailed with both simulation and experimental studies. Systematic descriptions of basic POELC, variable-frequency ZVS-POELC, and fixed-frequency ZVS-POELC make an impact on the understanding of related concepts by the researchers in this field. At high switching frequencies, these hard-switched converters suffer from high switching stress, high switching power losses, reduced reliability and electromagnetic interference (EMI) [5]. To overcome these difficulties, soft-switching techniques like zero-voltage switching (ZVS) have been introduced in LCs [6][7][8]. The ZVS technique expunges the large capacitance of the main switch through resonant switching, which minimizes the losses, as well as reduces the ringing in waveforms [9]. The soft-switching technique in LC has helped in escalating the switching frequency, hence casting a compact converter of a higher power density than that of the PWM converters [3]. ZVS was easier in high-current applications, and a reasonably low EMI has been observed [3]. Even though the frequency of switching is reasonably increased, the voltage stress across the main switch is also increased. In ZVS, the voltage across the main switch can reach eleven times the input voltage [9]. The voltage regulation in ZVS-LC is more liberally achieved by variable frequency operation [6]. The variable frequency operation results in high voltage stress on switches (hence the minimal reliability of power switches) and complexity of filter design. This paper proposes a modified topology to support the fixed-frequency ZVS in overcoming the abovementioned issues of the positive output elementary Luo converter (POELC). The main idea of the modified topology is adding an auxiliary switch across the resonant inductance, which delays the immediate resonant cycle until its turned OFF. Using variable pulse

The pulse width modulation (PWM) strategy employed in the voltage source inverter (VSI) not only control the magnitude of the output voltage but also the quality. Performance evaluations of such strategies are done in terms of fundamental voltage, total harmonic distortion (THD), switching losses etc. (primary indices) and also in terms of acoustic noise, electromagnetic interference (EMI), harmonic spread factor, distribution of harmonic power etc. (secondary indices). Multilevel inverter (MLI) has become unanimous choice in medium and high power applications due to their superior performance compared to three level inverters. The conventional Sub-Harmonic PWM (SHPWM) scheme and its variations offer the output voltage spectrum with high intensity harmonic components around the switching frequency; it will end with cluster harmonic with high acoustic noise. The first objective of this paper is to investigate harmonic spreading effects of existing multilevel inverter (MLI) strategies. Secondly the developing innovative PWM strategies for MLIs based on modified reference and carrier functions, which were proved for superior the primary indices at three-level VSI. Thorough simulation study of Pulse width modulation strategies such as SHPWM, inverted sine carrier PWM, MWM PWM, third harmonic injection PWM, triplen harmonic injection PWM, analog space vector PWM, trapezoidal PWM and discontinuous PWM for a cascaded multilevel inverter, are presented with results of primary and secondary indices. Hence, the PWM strategies of MLI are evaluated for harmonic spreading effect first time and a guide line for a beginner to select the PWM scheme for MLI fed drive systems is stenciled.

-A two stage ac drive configuration consisting of a single-phase line commutated rectifier and a three-phase voltage source inverter (VSI) is very common in low and medium power applications. The deterministic pulse width modulation (PWM) methods like sinusoidal PWM (SPWM) could not be considered as an ideal choice for modern drives since they result mechanical vibration and acoustic noise, and limit the application scope. This is due to the incapability of the deterministic PWM strategies in sprawling the harmonic power. The random PWM (RPWM) approaches could solve this issue by creating continuous harmonic profile instead of discrete clusters of dominant harmonics. Insufficient filtering at dc link results in the amplitude distortion of the input dc voltage to the VSI and has the most significant impact on the spectral errors (difference between theoretical and practical spectra). It is obvious that the sprawling effect of RPWM undoubtedly influenced by input fluctuation and the discrete harmonic clusters may reappear. The influence of dc link fluctuation on harmonics and their spreading effect in the VSI remains invalidated. A case study is done with four different filter capacitor values in this paper and results are compared with the constant dc input operation. This paper also proposes an ingenious RPWM, a ripple dosed sinusoidal referencerandom carrier PWM (RDSRRCPWM), which has the innate capacity of suppressing the effect of input fluctuation in the output than the other modern PWM methods. MATLAB based simulation study reveals the fundamental component, total harmonic distortion (THD) and harmonic spread factor (HSF) for various modulation indices. The non-ideal dc link is managed well with the developed RDSRRCPWM applied to the VSI and tested in a proto type VSI using the field programmable gate array (FPGA). Keywords:Ripple dosed sinusoidal reference random carrier pulse width modulation (RDSRRCPWM), Random pulse width modulation (RPWM), Harmonic spread factor (HSF), Voltage source inverter (VSI).