Nowadays, the DC-DC converter digital control is more attracted due to its benefits, like programmability, enhanced control algorithms. As a vital part of digital control, the digital pulse width modulator (DPWM) is designed to satisfy various requirements for higher performance. The existing digital pulse width modulator architecture activated with higher resolution along higher switching frequency, also the mandatory counter clock frequency is higher. To overcome this issue, the hybrid digital pulse width modulator architecture is proposed that combines Reversible Synchronous Sequential Counter and synchronous phaseshifted circuit. The proposed architecture consists of 4 blocks, they are, decoder, synchronous reversible counter, Synchronous Phase-Shifted Circuit, Delay line. The decoder is used to divide the input duty cycle command (DCC) into three parts: most significant bits (MSB), secondary significant bits (SSB) and least significant bits (LSB). The Reversible synchronous counter is used to count trigger signal in every clock period. Here, synchronous phase shift circuit is utilized to select the clock through the quadrant phase-shifted clocks. The delay line is used to set the time resolution of DPWM. In this work, D-Flip flop is used to leave sufficient slack among the set signal and reset signal for averting glitch. It can achieve high linearity resolution together with time resolution. The coding is done in Verilog and the proposed synchronous counter design has been synthesized using Xilinx ISE. Here, the assessment metrics, such as path delay, linearity, output duty cycle and time resolution are analyzed. The performance of the proposed SCD-MCT-MCF design shows higher output cycle 26.75%, 29.93% is compared with the existing design such as high resolution DPWM depending on synchronous phase-shifted circuit and delay line (Hyb DPWM-SPSE-DL), Delay-Line DPWM Architecture with Compensation Module and Delay-Adjustable Unit depending on Delay Line (Hyb DPWM-DLP) respectively.

No abstract

Nowadays, the DC-DC converter digital control is more attracted due to its benefits, like programmability, enhanced control algorithms. As a vital part of digital control, the digital pulse width modulator (DPWM) is designed to satisfy various requirements for higher performance. The existing digital pulse width modulator architecture activated with higher resolution along higher switching frequency, also the mandatory counter clock frequency is higher. To overcome this issue, the hybrid digital pulse width modulator architecture is proposed that combines Reversible Synchronous Sequential Counter and synchronous phase-shifted circuit. The proposed architecture consists of 4 blocks, they are, decoder, synchronous reversible counter, Synchronous Phase- Shifted Circuit, Delay line. The decoder is used to divide the input duty cycle command (DCC) into three parts: most significant bits (MSB), secondary significant bits (SSB) and least significant bits (LSB). The Reversible synchronous counter is used to count trigger signal in every clock period. Here, synchronous phase shift circuit is utilized to select the clock through the quadrant phase-shifted clocks. The delay line is used to set the time resolution of DPWM. In this work, D-Flip flop is used to leave sufficient slack among the set signal and reset signal for averting glitch. It can achieve high linearity resolution together with time resolution. The coding is done in Verilog and the proposed synchronous counter design has been synthesized using Xilinx ISE. Here, the assessment metrics, such as path delay, linearity, output duty cycle and time resolution are analyzed. The performance of the proposed SCD-MCT-MCF design shows higher output cycle 26.75%, 29.93% is compared with the existing design such as high resolution DPWM depending on synchronous phase-shifted circuit and delay line (Hyb DPWM-SPSE-DL), Delay-Line DPWM Architecture with Compensation Module and Delay-Adjustable Unit depending on Delay Line (Hyb DPWM-DLP) respectively.