Rapid thermal processing chemical vapor deposition (RTPCVD) has received considerable attention because of its ability to reduce-many of the processing problems associated with thermal exposure in conventional chemical vapor deposition, while still retaining the ability to grow high-quality epitaxial layers. In this paper, silicon homoepitaxy growth by RTPCVD is studied extensively and comprehensively. The principles of the RTPCVD system are described, followed by results of experiments on in situ cleaning, undoped Si epitaxy on Si and silicon-on-insulator substrates, in situ doped Si epitaxy, and selective epitaxial growth of Si using oxide masks and oxide on polycrystalline Si on oxide masks. Selective growth was achieved without the use of HC1. Our results show that RTPCVD is capable of growing high-quality, epitaxial Si layers with sharp dopant transition profiles. A brief discussion of fabricated devices is included.As individual semiconductor device dimensions continue .to shrink, stringent control of the vertical profiles of layers and dopants on an atomic scale without sacrificing control of microscopic lateral dimensions over large areas is required. Therefore, the ability to process layers of heterogeneous materials (metals, insulators, and semiconductors) without destroying previously fabricated structures is of paramount importance for advances in planar integration and may eventually make possible the development of true three-dimensional integration.

In this paper we have developed a SALICIDE process for CMOS applications using ion beam mixing for silicide formation and doped silicide in conjunction with RTA drive-in for shallow silicided junction formation, and have investigated the fundamental issues related to this process. Specifically, we have studied (i) the effects of ion beam mixing and RTA on the properties of Ti SALICIDE and the interaction between Ti and SiO2; (ii) the self-aligned TiN~OJTiSi2 formation and phase transformation; (iii) the mechanism of impurity redistribution and segregation, and junction formation during RTA drive-in; and (iv) the performances and reliability of fabricated SALICIDE devices. Results show that this process may have a great impact on future VLSI technology.

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A self-aligned titanium silicide process which combines the use of ion-beam mixing and rapid thermal processing (RTP) has been developed for CMOS VLSI applications. Shallow silicided junctions are formed by implanting dopants into silicide layers previously formed by ion-beam mixing with Si ions and low temperature annealing, and the subsequent drive-in of the implanted ions into the Si substrate during high temperature RTP. In addition, the formation of TiN on TiSi2 is achieved simultaneously during this process as a diffusion barrier for Al metallization. Short-channel MOS transistors with SALICIDE structure have been successfully fabricated and tested. Results of the impurity diffusion in silicide layer, the impurity segregation at both silicide/Si and oxide/silicide interfaces, contact stabilit of Al/TiN/TiSi2 structure, and device characteristics will be reported. Issues related to this process and its application to submicron device fabrication are discussed and foreseeable problem areas identified.