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With the advancement in technologies, data storage has become crucial for low power applications. Static random access memory (SRAM) is popular for its fast access of data but it is prone to high power dissipation. Adiabatic logic is one of the techniques which have proven to reduce the energy consumed by the circuit per operation. A novel adiabatic SRAM cell has been proposed in this paper. The proposed cell resembles the operation of the conventional 6T SRAM cell. The latch of the SRAM cell has been modelled using split level charge recovery logic (SCRL). The proposed circuit is simulated using Cadence Virtuoso (180nm) and it is compared with the conventional 6T SRAM cell. The proposed SRAM cell consumes 8.7 times less power as compared to the conventional 6T SRAM cell at 100MHz.

The approximate hardware design can save huge energy at the cost of errors incurred in the design. This article proposes the approximate algorithm for low-power compressors, utilized to build approximate multiplier with low energy and acceptable error profiles. This article presents two design approaches (DA1 and DA2) for higher bit size approximate multipliers. The proposed multiplier of DA1 have no propagation of carry signal from LSB to MSB, resulted in a very high-speed design. The increment in delay, power, and energy are not exponential with increment of multiplier size ( n ) for DA1 multiplier. It can be observed that the maximum combinations lie in the threshold Error Distance of 5% of the maximum value possible for any particular multiplier of size n . The proposed 4-bit DA1 multiplier consumes only 1.3 fJ of energy, which is 87.9%, 78%, 94%, 67.5%, and 58.9% less when compared to M1, M2, LxA, MxA, accurate designs respectively. The DA2 approach is recursive method, i.e., n -bit multiplier built with n/2-bit sub-multipliers. The proposed 8-bit multiplication has 92% energy savings with Mean Relative Error Distance (MRED) of 0.3 for the DA1 approach and at least 11% to 40% of energy savings with MRED of 0.08 for the DA2 approach. The proposed multipliers are employed in the image processing algorithm of DCT, and the quality is evaluated. The standard PSNR metric is 55 dB for less approximation and 35 dB for maximum approximation.

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