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Abstract-This paper describes a bidirectional, differential, 16 Gb/s per link memory interface that includes a Controller and an emulated DRAM physical interface (PHY) designed in 65 nm CMOS. To achieve high data rate, the interface employs the following technology ingredients: asymmetric equalization, asymmetric timing calibration, asymmetric link margining, inductor based (LC) PLLs, multi-phase error correction, and a data dependent regulator. At 16 Gb/s, this interface achieves a unit-interval to inverter FO4 ratio of 2.8 (Controller) and 1.4 (DRAM) and operates in a channel with 15 dB loss at Nyquist. Under such bandwidth limitations on and off chip, the Controller and DRAM PHYs consume 13 mW/Gb/s and 8 mW/Gb/s, respectively. Using PRBS 2 11 1, the link achieves a timing margin of 0.19 UI at a BER of 1e-12 for both read and write operations.

A quad high-speed transceiver cell is designed and implemented in 0.l3pm CMOS technology. To achieve low jiner while maintaining low power consumption, dual on-chip regulators are used for each dualloop PLL. The prototype chip demonstrates that the links can operate from 400Mb/s to 4GbIs with a bit enor rate < The quad cell consumes 390mW at 2.5Gb/s (95mW/link) under typical operating conditions with a 400mV output swing driving double terminated links.

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This paper describes a 16-Gb/s differential bidirectional I/O transceiver cell in an emulated 40nm DRAM process that has a fan-out of four inverter delay (FO4) of 45ps, resulting in a bit time that is only 1.4 FO4 delays long. The transceiver implements several techniques to achieve low jitter despite the slow process and constrained power consumption, including a quad rate clocking with closed-loop quadrature correction, a shared LC-PLL with an octagonal inductor in a three-metal process, and a data-dependent regulator. The transceiver has measured random jitter of 380fs rms at the transmitter output and BER < 10 -14 while consuming 8mW/Gb/s. Introduction The top-level transceiver architecture is shown in Fig. 1 with a companion controller [1] implementing equalization and per bit slice skew calibration. The DRAM transceiver uses a quad rate clocking scheme to circumvent high gate delay (FO4), a quadrature corrector to minimize phase error in the I & Q clocks, an LC-PLL to achieve low random jitter (RJ), a data-dependent regulator to minimize power-supply induced jitter (PSI-J) in the data path, and CML signaling to minimize PSI-J in the clock path. This I/O cell is implemented in a 65nm process with design restrictions to emulate a projected 40nm DRAM process, expected to be available in 2010. Process Emulation Critical parameters in a projected 40nm DRAM process node are shown in the first two columns of Table 1 [2]. Note that periphery I/O transistors have larger minimum channel length than core transistors and that only 3 metal layers are available. These parameters are emulated using a 65nm process, as shown in the third column of Table 1. The worst-case FO4 delay is emulated using high Vt device with a +10nm gate length bias (L drawn = 70nm versus 60nm). The DRAM thick metal layer is emulated by stacking M3-M5.Clocking and Quadrature Corrector Low jitter, critical for 16-Gb/s operation (UI=62.5ps), is achieved with a supply-regulated LC-PLL operating from a 500-MHz reference. The PLL contains an 8-GHz LC-VCO followed by a quadrature divide-by-two circuit to generate 4-GHz quadrature clocks (Fig. 2). Despite a limited inductor Q of ~3.5 due to lossy metal resistance, the LC-VCO achieves better phase noise performance -proportional to Q 2 -relative to a ring-based VCO for a given power budget. The 0.75-nH inductor is constructed with an octagonal differential structure for maximum Q over area ratio and has a self-resonant frequency of 30GHz. The inherent low K VCO of the LC-based design suppresses reference spurs and reduces loop filter phase noise. Supply regulation for the LC-VCO reduces PSI-J caused by the high multiplication ratio. To relax the headroom requirement for supply regulation, an NMOS-only cross-coupled pair is used as a negative transconductance element. The higher gm/C of the NMOS design (relative to PMOS) also reduces fixed tank capacitance and improves tuning range. The VCO frequency is set by a fine analog varactor control and a coarse digital switching of MOM capacitors for exte...