A new algorithm is presented that combines performance and variation objectives in a behavioural model for a given analogue circuit topology and process. The tradeoffs between performance and yield are analysed using a combination of a multi-objective evolutionary algorithm and Monte Carlo simulation. The results indicate a significant improvement in overall simulation time and efficiency compared to conventional simulation based approaches, without a corresponding drop in accuracy. This approach is particularly useful in the hierarchical design of large and complex circuits where computational overheads are often prohibitive. The behavioural model has been developed in Verilog-A and tested extensively with practical designs using the Spectre™ simulator. A benchmark OTA circuit was used to demonstrate the proposed algorithm and the behaviour has been verified with transistor level simulations of this circuit and a higher level filter design. This has demonstrated that an accurate performance and yield prediction can be achieved using this model, in a fraction of the time of conventional simulation based methods.

A new approach in hierarchical optimisation is presented which is capable of optimising both the performance and yield of an analogue design. Performance and yield trade offs are analysed using a combination of multiobjective evolutionary algorithms and Monte Carlo simulations. A behavioural model that combines the performance and variation for a given circuit topology is developed which can be used to optimise the system level structure. The approach enables topdown system optimisation, not only for performance but also for yield. The model has been developed in VerilogA and tested extensively with practical designs using the Spectre simulator. A benchmark OTA circuit is used to demonstrate the behavioural model development and a 7 th order video filter has been designed to demonstrate hierarchical optimisation at the system level. The results have been verified with transistor level simulations and suggest that an accurate performance and yield prediction can be achieved with the proposed algorithm.

Abstract-A novel technique is proposed in this paper that achieves a yield optimized design from a set of optimal performance points on the Pareto front. Trade-offs among performance functions are explored through multi-objective optimization and Monte Carlo simulation is used to find the design point producing the best overall yield. One advantage of the approach presented is a reduction in the computational cost normally associated with Monte Carlo simulation. The technique offers a yield optimized robust circuit design solution with transistor level accuracy. An example using an OTA is presented to demonstrate the effectiveness of the work.

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