Many signal and image processing applications will be more benefited if the transform gives good spectral and temporal resolution in arbitrary regions of the timefrequency plane that is provided by the Discrete Wavelet Packet Transform (DWPT). In this paper, the architecture for lifting scheme based Daubechies 9/7 wavelet is proposed. The proposed architecture performs both forward and inverse transform. The architecture does not require any extra memory/FIFOs to store the intermediate results. The proposed architecture is verified by performing DWPT for images of size 64x64. The architecture has been described in VHDL at the RTL level and simulated successfully using ModelSim simulation environment.

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The best-basis algorithm has gained much importance on textured-based image compression and denoising of signals. In this paper, an architecture for the wavelet-packet based best-basis algorithm for images is proposed. The paper also describes the architecture for best-tree selection from 2D wavelet packet decomposition. The precision analysis of the proposed architecture is also discussed and the result shows that increase in the precision of input pixel greatly increases the Signal-to-Noise Ratio (SNR) per pixel whereas increase in the precision of filter coefficient does not greatly help in improving the SNR value. The proposed architecture is described in VHDL at the RTL level, simulated successfully for its functional correctness and implemented in an FPGA.

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In this work, we propose an architecture for the waveletpacket based best-basis algorithm for images using Shannon Entropy as cost function. The algorithm for the logarithm implementation for integers using Taylor series is also proposed to implement Shannon entropy. The proposed architecture includes the architectures for the best-tree selection. The execution time of the proposed hardware for the best-basis algorithm for images is compared to its software implementation. The proposed best-basis architecture has been described in VHDL at the RTL level, simulated successfully for its functional correctness and implemented in an FPGA.