This paper describes a technique for the monitoring and control of the reflow soldering process. The technique combines state‐of‐the‐art infra‐red (IR) sensor technology, coupled with application‐specific process monitoring and control software, providing a unique capability both to monitor product temperatures during processing and to modify the process settings. The development of techniques to allow variation of the heat transfer from the oven to the in‐process printed circuit assemblies (PCAs) provides the means to adjust the soldering oven’s process settings for each individual PCA. This automatic profiling ensures consistent thermal histories and optimises oven energy consumption. Archiving of the reflow profiles along with temperatures recorded for each PCA provides full traceability to the reflow process settings for each individual PCA. The incorporation of IR sensing technology also provides a means to monitor the performance of the process.

• This is a conference paper and the definitive version is also available at: http://ieeexplore.ieee.org. Personal use of this material is permitted.However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. ABSTRACTPrevious models of the reflow soldering process have used commercial finite difference (FD) or computational fluid dynamics simulation software to create detailed representations of the product and/or the reflow furnace. Such models have been shown to be highly accurate at predicting the temperatures a PCB design will achieve during the reflow process. These models are however complex to generate and analysis times are long, even using modern high performance workstations. With the move to adopt lead free soldering technology, and the consequently higher reflow process temperatures, optimisation of the reflow profile is gaining a renewed emphasis. This paper describes a less complex approach to modelling of the process, which uses simplified representations of both the product and the process, together with a FD solver developed specifically for this application, and which achieves an accuracy comparable with more detailed models. In order t o establish an accurate representation of the specific reflow furnace being simulated, a reflow logger is used to make measurements of the temperature and level of thermal convection at each point along the length of the furnace for a small number of carefully chosen reflow profiles. The temperatures for any other reflow profile can then be predicted from these measurements.

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PurposeRouting efficiency provides an estimate of the compactness of a specific PCB layout in comparison with the theoretical minimum size for the circuit design. This work describes a methodology for estimating the routing efficiency of existing PCB layouts from scanned images of either a manufactured PCB or the relevant PCB artwork. Measuring and maximising routing efficiency offers a powerful tool in the drive to minimise the size and cost of a PCB, as it provides a quantitative measure of the need to include costly features such as multiple signal layers and blind (or partial) vias.Design/methodology/approachThe methodology was proven as a manual method, before implementation as a software tool. This work describes the image processing techniques used to recognise traces and vias and describes how this information is processed to derive substrate utilisation statistics.FindingsAn initial survey suggests that trace routing efficiency has declined through time, indicating that many layouts are larger than necessary, or use more signal layers than are required by routing constraints alone.Research limitations/implicationsThis work finds that digital logic circuits follow a more coherent trend than analogue or mixed technology circuits. The results are therefore much more applicable in the digital domain.Practical implicationsAs the methodology is implemented using images of PCB layouts, it offers the potential to investigate the performance of routing capability for current and legacy applications where CAD data are not available.Originality/valueWhere CAD drawings exist, routing efficiency can easily be calculated from the data. However, the methodology for estimating routing efficiency retrospectively from circuit images is believed to be unique, and sidesteps the problems of gaining access to this information.