This paper discusses an optical packet switch (OPS) arch itecture, which utilizes the components like optical reflectors, tunable wavelength converters (TWCs), arrayed waveguide grating (AW G) and pieces of fiber to realize the switching action. This architecture uses routing pattern of AW G, and its symmetric nature, to simp lify switch operation significantly. It is also shown that using multiwavelengths optical reflector, length of delay lines can be reduced to half of its original value. Th is reduction in length is useful for comparat ively larger size packets as for them. It can grow up some kilo meters. The considered architecture is compared with already published architecture. Finally, modifications in the architecture are suggested such that switch can be efficiently placed in the backbone network.

Optical packet switching is considered as next generation data transfer technology in conjunction with mature electronics. In the design of optical routers, the main issue is the splitting loss of the devices and control unit complexity. Hence, much research has been done in designing of the simple routers. This exploration leads to generation of AWG based optical routers. In this paper, AWG based optical router is discussed and simulation results are presented in terms of packet loss probability for symmetric and asymmetric switch. It is also shown that in the earlier architecture, due to the unequal power of the buffered and directly transmitted packets, some of the buffered packet may not fully utilize the buffer capacity due to the degraded quality of the packets in the buffer. However, in the modified architecture, the buffer capacity is fully utilized effectively.

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In this paper, an optical packet switch architecture which is realized with a very few components is discussed. The main advantage of this architecture is its simple buffering structure. The performance of optical packet switch architecture in terms of packet loss probability and average delay is presented. The obtained results clearly show that the considered architecture provides very low packet loss probability with reasonably low average delay.

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