This research applies formal dataflow analysis and techniques to high-fevel DFT. Our proposed approach improves testability of the behavioral-level circuit description {such as in VHDL) F e d on propagation of the value ranges of variables throtigh the circuit's Control-Data Flow Graph {CDFG). The resulting testable circuit is accomplished via controllability land observability computations from these value ranges dnd insertion of appropriate testability enhancements, while keeping the design area-performance overhead to a hinimum. I IntrodJctionTraditionally, P S I design and test processes have been kept separate, ;with test considered only at the end of the design cycle. However, in contemporary design flows, test merges with design much earlier in the process, creating a design-for-test\(DFT) process flow, the goal of which is to produce hierarFhically testable designs. A design is said to be hierarchically testable, if the input (output) ports of every module in Ithe design hierarchy, are easily controllable (observable) through system inputs (outputs) [I].Classical DFT strategies have been conventionally limited to the end of the design phase, when a detailed gatelevel description of the design is available [6, 7, 81. Testability featured that are incorporated into the design at the post-synthesis step result in area and delay penalties. These stTuctural testability enhancement techniques fall into the following categories: Built-in self-test (BIST), non-scan and (scan-based DFT. In general, the amount of scan required to get an acceptable fault coverage varies from design t? design. At-speed testing of a circuit is not possible whenlscan tests are used, due to scanning in and out of flip-flopI values.Recent studies [l, 2, 3, 4, 5, 13, 151 have shown that if testability is not addressed during behavioral synthesis, many modules and registers in the resultant registertransfer-level CRTL) circuit may not be testable for the operations and/or variables mapped to them. The problem is exacerbated in the presence of loops, constants and ret convergent fanout in the control-data flow graph (CDFG) corresponding1 to the design.In [9], the' authors proposed a partial-scan selection I mechanism that works on the CDFG of a design derived I I I I I I I l from its behavioral description. Hard-to-test areas of the design are identified by the evaluated controllability and observability measures, and test point insertion techniques such as those described in [5] are applied. Lastly, flip-flops corresponding to variables that are hard to control and observe are selected for partial-scan to maximize the impact on testability of the design. The controllability measures obtained in this fashion, however, do not consider the value ranges of the variables and the probabilities of propagating these value ranges to the nodes in the CDFG. In [17], the authors propose a behavioral testability enhancement technique based on the analysis of values and variable probabilities obtained from profiling of the high-level description. The si...

We describe a library of parameterized 'VHDL models for various concurrent fault detection circuits and maintenance functions developed for simulation and synthesis of ASICs which support on-line testing and diagnostics in systems designed for high reliability and availabiility. Issues associated with the selection and modeling of the varicus online testing functions are also discussed.

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The focus of this research is on the testability analysis of the operators in the behavioral description prior to synthesis. The controllabilities of the inputs to an operator and the observabilities of the outputs of the operation are computed from the value ranges of the variables that serve as the inputs and outputs. The proposed technique uses a formal dataflow analysis instead of profiling or simulation, to accurately pin-point the hard-to-test operations i n the design. Variable selection for testability enhancement of hard-to-test operations is accomplished based on the computed testability measures for all the involved operations in the behavioral description. The insertion of appropriate testability enhancements is then performed for the hard-to-test operators to achieve significantly higher test coverages, while keeping the design area-performance overhead to a minimum.

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