The study develops a new topology for a single phase cascaded H-bridge multilevel inverter (CHBMLI) with a focus to reduce the number of power switching devices in the path for the flow of current. The philosophy combines an array of series connected voltage sources on either side of an H-bridge inverter to derive the new configuration for the MLI. It allows a multicarrier pulse width modulation approach to the process of generating the pulses for synthesising the PWM output voltage. The use of a smaller number of switches to reach the output voltage show cases the ability of the modular architecture to expand the scope of the CHBMLI. The architecture of a field programmable gate array fosters to realise its implementation and validate the simulated results over a range of modulation indices. The performance draws a new directive in the choice of a particular topology for the MLI to suit applications in the real world.

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A new single-phase H-bridge multilevel inverter (MLI) topology constructed using auxiliary reverse-connected voltage sources along with a hybrid pulse width modulation (PWM) strategy is proposed, to extract a variable frequency variable amplitude output voltage. The principle eschews an astute philosophy to employ PWM approach only for a particular Hbridge that serves to produce the desired level while the remaining add-on modules function with the theory of fundamental switching. It involves the use of reduced number of switching devices for a specific number of output voltage levels in comparison with conventional MLIs. The design of the hybrid PWM suitable to power the appropriate switches add strength to its formulation in the sense it requires only either addition or subtraction to generate the square wave modulated pulses for the power devices in the other units other than that responsible for offering the preferred level of output voltage. The MATLAB R2010b-based simulated performance adequately validated through experimental results foresee the emergence of a new variety of MLIs and forge a different dimension for inverter interfaces in power control applications.

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This study develops a pulse width modulation (PWM) strategy with a view to achieve explicit control of voltage and accrue a minimum total harmonic distortion in a multilevel inverter (MLI) of any preferred level. The multi objective digital formulation tailors to facilitate discrimination of pulses for various levels and equalise the switching losses in all the power switches in the MLI. The philosophy of the method centres to calculate the pulses for the desired target fundamental output voltage based on equal area criteria. It excludes the need for a carrier in the generation of the PWM pulses through a process of matching the output level with the sectionalised dc levels and travels to determine the switching instants using mathematical relations. It includes simulation results from a MATLAB platform for a seven level MLI and avails the use of a field programmable gate array-based prototype to validate the findings.