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This paper describes the development of a 520 terminal Plastic Ball Grid Array (PBGA) package to meet the system level requirements of the UltraSPARC-ITM microprocessor. The Printed Circuit Board (PCB) substrate PBGA package developed was designed to handle chip operation above 200 MHz and dissipate 36 watts of power with the assistance of an integral heat sink and airflow. Mechanical stresses, board level reliability, thermal and electrical requirements are outlined.The package enhancements and process refinements executed to meet the design goals and reliability requirements are presented.

Next generation single and multichip packages must support flip chip assembly of die with a very high mmber of I/O. Cofire ceramic techlogy has been the truditional solution. We report on a new pchging technology that, in many ways, is an organic version Cofire ceramic. This "Colamination" process leverages recent developments in adhesiveless flex circuitry and law temperature sinterable materials to produce multilayer structures with sintered blind and buried vias in a single lamination step. This paper describes the fabrication of a 6-metal layer 751 I/O flip chip test vehicle with the Colamination process. Novaclap flex circuit layer pairs, V i a p i ' 'bond ply layers, and a metal stiffener are colaminated to form the package substrate.The package design takes advantage of Novacl& design rules, which includes microvias in die attach and BGA p d . Test vehicle design, subsfrate fabrication, flip chip assembiy, thermomechanical, and environmental test results are described

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