No abstract

Long-term EEG monitoring is an important tool used for the diagnosis of epilepsy. Truly Wearable EEG can be considered as the future of ambulatory EEG units, which are the current standard for long-term EEG monitoring. Replacing these short lifetime, bulky units with long-lasting miniature and wearable devices which can easily be worn by patients will result in more EEG data being acquired for longer monitoring periods. This paper presents an analog based data reduction integrated circuit that would reduce the amount of power required to transmit EEG data by identifying the sections of data that are interesting for diagnostic purposes while discarding background activity. Using the data reduction system as part of a miniature wireless EEG monitoring unit would yield significant reductions in power consumption since the transmitter will only be switched on based on the data reduction system output.A system prototype chip has been fabricated in a 0.35 µm CMOS process. The system consumes 760 nA from a 1.25 V supply and is able to achieve a sensitivity of 87% while transmitting 45% of the overall EEG data.

Abstract-This paper describes a full system-on-chip to automatically detect sleep spindle events from scalp EEG signals. These events, which are known to play an important role on memory consolidation during sleep, are also characteristic of a number of neurological diseases. The operation of the system is based on a previously reported algorithm which used the Teager Energy Operator (TEO), together with the Spectral Edge Frequency (SEF50) achieving over 70% sensitivity and 98% specificity. The algorithm is now converted into a hardware analog based customized implementation in order to achieve extremely low levels of power. Experimental results prove that the system, which is fabricated in a 0.18 µm technology, is able to operate from a 1.25 V power supply consuming only 515 nW, with an accuracy which is comparable to its software counterpart.

Long-term monitoring of epilepsy patients requires low-power systems that can record and transmit electroencephalogram data over extended periods of time. Since seizure events are rare, long-term monitoring inherently results in large amounts of data that are recorded and hence need to be reduced. This paper presents an ultra-low power integrated circuit implementation of a data reduction algorithm for epilepsy monitoring, specific to seizure events. The algorithm uses line length of the electroencephalogram signals as the key discriminating feature to classify epochs of data as seizure or non-seizure events. It is implemented in AMS 0.18-µm CMOS technology and its output is connected to a Bluetooth low energy transceiver to wirelessly transmit potential seizure events. All the modules of the algorithm have been implemented on chip to use a small number of clock cycles and remain mostly in an idle mode. The algorithm, on the chip, achieves 50% of data reduction with a sensitivity of 80% for capturing seizure events. The overall power consumption of the chip is measured to be 23 µW, while the full system with wireless transmission consumes 743 µW. The results in this paper demonstrate the feasibility of a long-term seizure monitoring system capable of running autonomously for over two weeks.

Epilepsy is one of the most common serious brain disorders affecting 1% of the world population. Epileptic seizure events are caused by abnormal excessive neuronal activity in the brain, which may be associated with behavioural changes that severely affect the patients' quality of life. These events are manifested as abnormal activity in electroencephalography (EEG) recordings of individuals with epilepsy. This paper presents the on-chip implementation of an algorithm that, operating on the principle of data selection applied to seizures, would be able to reduce the power consumption of EEG devices, and consequently their size, thereby significantly increasing their usability. In order to reduce the power consumed by the on-chip implementation of the algorithm, mathematical approximations have been carried out to allow for an analog implementation, resulting in the power consumed by the system to be negligible in comparison to other blocks in an EEG device. The system has been fabricated in a 0.18 µm CMOS process, consumes 1.14 µW from a 1.25 V supply and achieves a sensitivity of 98.5% while only selecting 52.5% of the EEG data for transmission.