Noise filtering and image enhancement are two active areas of research in signal processing. For the time of signal acquisition and transmission, impulse noise may corrupt the digital data. To overcome this, switching median filters are generally used which consist of impulse detection and noise filtering. In this paper, an efficient decision tree based denoising technique and a high performance architecture for FPGA prototyping is presented for the elimination of random valued impulse noise. To identify noise pixels, we propose a new tree based impulse noise detector. The proposed architecture make use of parallel computation by splitting the input image in to odd and even index pixel masks. An additional performance enhancement is achieved by introducing pipelining between processing stages. The design is implemented using XILINX ISE 14.1 for Virtex 5 ML507 FPGA platform which can operate at 106 MHz clock frequency. The proposed method outperforms the existing denoising techniques in terms of image quality as shown by the simulation results.