A family of CMOS-based active pixel image sensors (APS's) that are inherently compatible with the integration of onchip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-m CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistortransistor logic (TTL) compatible control signals. Methods of on-chip suppression of fixed pattern noise to less than 0.1% saturation are demonstrated. The baseline design achieved a pixel size of 40 m2 40 m with 26% fill-factor. Array sizes of 28 2 28 elements and 128 2 128 elements have been fabricated and characterized. Typical output conversion gain is 3.7 V/e 0 for the p-well devices and 6.5 V/e 0 for the n-well devices. Input referred read noise of 28 e 0 rms corresponding to a dynamic range of 76 dB was achieved. Characterization of various photogate pixel designs and a photodiode design is reported. Photoresponse variations for different pixel designs are discussed. Index Terms-Active pixel sensor, cameras, CMOS image sensor. I. INTRODUCTION I N many imaging systems, integration of the image sensor with circuitry for both driving the image sensor and performing on-chip signal processing is becoming increasingly important. A high degree of electronics integration on the focal-plane can enable miniaturization of instrument systems and simplify system interfaces. In addition to good imaging performance with low noise, no lag, no smear, and good blooming control, it is desirable to have random access, simple clocks, and fast readout rates. The development of a CMOScompatible image sensor technology is an important step for highly integrated imaging systems since CMOS is well suited for implementing on-chip signal processing circuits. CMOS is also a widely accessible and well-understood technology.

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Abstract-A CMOS imaging sensor is described that uses active pixel sensor (APS) technology and permits the integration of the detector array with on-chip timing, control, and signal chain electronics. This sensor technology has been used to implement a CMOS APS camera-on-a-chip. The camera-on-a-chip features a 256 x 256 APS sensor integrated on a CMOS chip with the timing and control circuits, and signal-conditioning to enable random-access, low power ("5 mW) operation, and low read noise (13 e-rms). The chip features simple power supplies, fast readout rates, and a digital interface for commanding the sensor, as well as for programming the window-of-interest readout and exposure times. Excellent imaging has been demonstrated with the APS camera-on-a-chip, and the measured performance indicates that this technology will be competitive with charge-coupled devices (CCD's) in many applications.