Modular multilevel converters (MMCs), with their inherent features and advantages over other conventional converters, have gained popularity and remain an ongoing topic of research. Many scholars have solved issues related to the operation, control, protection, and reliability of MMCs using simulation software and small hardware prototypes. We propose a novel approach for an MMC controller design with real-time systems. By utilizing a key benefit of LabVIEW Multisim co-simulation, an MMC control algorithm that can be deployed on a field-programmable gate array (FPGA) was developed in LabVIEW. The complete circuit was designed in Multisim, and a co-simulation was performed to drive an MMC model. The benefit of this topology is that control algorithms can be designed in a LabVIEW FPGA and tested with the Multisim co-simulation circuit to obtain simulation results. Once the controller works and provides satisfactory results, the same algorithm can be deployed in any NI (National Instruments) FPGA-based controller, like a compact remote input/output (RIO), to control real-time MMCs designed in an NI PCI eXtensions for Instrumentation (PXI) system. This method saves time and provides flexibility for effectively designing control algorithms and implementing them in an FPGA for real-time model implementation.

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Modular Multilevel Converter (MMC) is an emerging converter topology for medium and high voltage applications. Nearest level Modulation (NLM) is the conventional control topology used to control the MMC that produces the N+1 AC output waveform. In previous research work, the Modified NLM has been already proposed, producing a 2N+1 and 4N+1 output waveform while utilizing a half-bridge (HB) submodule (SM) topology. However, half-bridge-based MMC has a similar behavior as two-level Voltage Source Converter (VSC) and cannot block DC fault current in case of DC-side short circuit fault. So, in recent years, full-bridge-based MMC topology is preferably used by manufacturers as it has DC fault blocking capabilities. This paper presents the Modified NLM for Full bridge (FB) SM topology to take the critical benefits of FB SM topology and improve power quality. The proposed method is simpler to implement and produces a 4N+1 AC output waveform. The THD of the output voltage and current reduces to half compared to the conventional NLM method. The proposed method is verified using LabVIEW Multisim co-simulation and as well as real-time simulation.INDEX TERMS Modified NLC, full bridge, HVDC MMC, hardware-in-loop simulation.

Integration of renewable energy resources and conventional grids leads to an increase in power quality issues. These power quality issues require different standards to be followed for accurate measurement and monitoring of various parameters of the power system. Conventional power quality analyzers (PQAs) are programmed to a particular standard and cannot be reconfigured by the end user. Therefore, conventional PQAs cannot meet the challenges of a rapidly changing grid. In this regard, a Compact RIO-based (CRIO-based) PQA was proposed, that can be easily reprogrammed and cope with the challenges faced by conventional PQAs. The salient features of the proposed PQA are a high processing speed, interactive interface, and high-quality data-storage capacity. Moreover, unlike conventional PQAs, the proposed PQA can be monitored remotely via the internet. In this research, a hardware-in-loop (HIL) simulation is used for performing the power-quality assessment in a systematic manner. Power quality indices such as apparent power, power factor, harmonics, frequency disturbance, inrush current, voltage sag and voltage swell are considered for validating the performance of the proposed PQA against the Fluke’s PQA 43-B.