In this paper, we present an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264 / MPEG4 Part 10 video coding standard. The hardware design is based on a novel organization of the intra prediction equations. This hardware architecture is designed to be used as part of a H.264 video decoder for portable applications. The proposed architecture is implemented in Verilog HDL. The Verilog RTL is verified to work at 70 MHz in a Xilinx II FPGA. The FPGA implementation can process a VGA frame (640x480) in the worst case in 9.85 msec.

In this paper, we propose a full rate space-time block code selection technique, which achieves full diversity when more than two transmit antennas are used for transmission. Only one or few feedback bits are needed at the transmitter, representing relative state information of the channels. Moreover, the proposed scheme allows separate decoding of transmitted symbols at the receiver. It is shown by computer simulations that, the new approach provides SNR improvement, especially when feedback errors occur, compared to the transmit antenna selection technique associated with Alamouti's scheme, for the same number of feedback bits.

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