Chip Multiprocessors (CMPs)

This paper describes an unconventional way to apply wireless networking in emerging technologies. It makes the case for using a two-tier hybrid wireless/wired architecture to interconnect hundreds to thousands of cores in chip multiprocessors (CMPs), where current interconnect technologies face severe scaling limitations in excessive latency, long wiring, and complex layout. We propose a recursive wireless interconnect structure called the WCube that features a single transmit antenna and multiple receive antennas at each micro wireless router and offers scalable performance in terms of latency and connectivity. We show the feasibility to build miniature on-chip antennas, and simple transmitters and receivers that operate at 100 − 500 GHz sub-terahertz frequency bands. We also devise new two-tier wormhole based routing algorithms that are deadlock free and ensure a minimum-latency route on a 1000-core on-chip interconnect network. Our simulations show that our protocol suite can reduce the observed latency by 20% to 45%, and consumes power that is comparable to or less than current 2-D wired mesh designs.

As chip multiprocessors scale to a greater number of processing cores, on-chip interconnection networks will experience dramatic increases in both bandwidth demand and power dissipation. Fortunately, promising gains can be realized via integration of Radio Frequency Interconnect (RF-I) through on-chip transmission lines with traditional interconnects implemented with RC wires. While prior work has considered the latency advantage of RF-I, we demonstrate three further advantages of RF-I: (1) RF-I bandwidth can be flexibly allocated to provide an adaptive NoC, (2) RF-I can enable a dramatic power and area reduction by simplification of NoC topology, and (3) RF-I provides natural

Power and bandwidth requirements have become more stringent for DRAMs in recent years. This is largely because mobile devices (such as smart phones) are more intensively relying on the use of graphics. Current DDR memory I/Os operate at 5Gb/s with a power efficiency of 17.4mW/Gb/s (i.e., 17.4pJ/b) [1], and graphic DRAM I/Os operate at 7Gb/s/pin [3] with a power efficiency worse than that of DDR. High-speed serial links [5], with a better power efficiency of 1mW/Gb/s, would be favored for mobile memory I/O interface. However, serial links typically require long initialization time (~1000 clock cycles), and do not meet mobile DRAM I/O requirements for fast switching between active, standby, self-refresh and power-down operation modes [4]. Also, traditional baseband-only (or BB-only) signaling tends to consume power super-linearly [4] for extended bandwidth due to the need of power hungry pre-emphasis, and equalization circuits.To overcome aforementioned technical limitations, we propose to implement a Dual (Base+RF) Band Interconnect (DBI) to enable high throughput data rate and low power operation in a mobile DRAM I/O interface. Unlike the conventional BBonly signaling, the proposed DBI signaling, as shown in Fig. 28.1.1, uses both BB and RF bands for simultaneous dual data stream communications, but shares the common transmission line (T-Line). Instead of limiting the baseband operation within its linear-power-consumption region versus the bandwidth, we can now double the interface bandwidth by using DBI and still maintain the linearpower-consumption versus the bandwidth in each of the dual bands. Additionally with forwarded clocking that adds a small overhead to DRAM I/O ( Fig. 28.1.1), the DBI enables simultaneous bidirectional data links [6] as well. By applying such links to DRAM I/O data (DQ) and command/address (C/A), we can greatly reduce the DRAM access time by requesting DRAM read/write-operations simultaneously. Consequently, we can implement bidirectional DRAM I/Os with a much higher aggregate data rate (up to 10Gb/s) and lower power operation (2.5mW/Gb/s).Figure 28.1.2 shows the DBI transceiver schematic of the memory controller side with an RF-band transmitter (RFTX) and a baseband receiver (BBRX). The RFTX contains an LC tank VCO, an amplitude-shift keying (ASK) modulator and a frequency-selective transformer. In RFTX, the VCO first generates RF carrier at 23GHz and continuously modulates M1 and M2 for ASK communication. The data stream D 1(RF) modulates the 23GHz carrier by switching on/off the current flow through M3 and M4 to complete the ASK modulation. The modulated output is then inductively coupled into an off-chip T-Line by way of an on-chip differential transformer. The BBRX amplifies the incoming data stream D 2(BB) using buffers with On-Die Termination (ODT) to set the common mode voltage at the transformer center tap and remove the impedance mismatch. As a result, we transmit and receive D 1(RF) and D 2(BB) data streams concurrently under both differential (RF-band) and common (BB) modes...

In the era of the nanometer CMOS technology, due to stringent system requirements in power and performance, microprocessor manufacturers are relying more on chip multi-processor (CMP) designs. CMPs partition silicon real estate among a number of processor cores and on-chip caches, and these components are connected via an on-chip interconnection network (Network-on-chip). It is projected that communication via NoC is one of the primary limiters to both performance and power consumption. To mitigate such problems, we explore the use of multiband RF-interconnect (RF-I) which can communicate simultaneously through multiple frequency bands with low power signal transmission and reconfigurable bandwidth. At the same time, we investigate the CMOS mixed-signal circuit implementation challenges for improving the RF-I signaling integrity and efficiency. Furthermore, we propose a micro-architectural framework that can be used to facilitate the exploration of scalable low power NoC architectures based on physical planning and prototyping.