No abstract

The hardware security issues are emerging in crypto-algorithms of embedded portable Internet-of-Things-Devices (IoTD). The communication protocols/standards including MQTT (Message Queuing Telemetry Transport) are enforcing additional cares in device-to-system design perspectives. Due to computation-capacity limitations (CCLs) in battery-operated IoTD, heavy-duty crypto-algorithms are prohibited. This results in compromised hardware using lightweight algorithms. In this study, a new implementation schema for hierarchically-connected IoTD for indoor applications is proposed. This schema allows the IoT network to utilise strong-crypto-algorithms (i.e. RSA) instead of lightweight algorithms (i.e. attribute-based encryption (ABE)). Therefore, without increasing the consumption power or complexity, the security in the IoT network increases. This method brings about a new low CCL RSA with two-folded power-aware implementation. Furthermore, without complexity overhead, the proposed method is more secure than the conventional implementation due to the inherent countermeasure against the side-channel attacks. The presented schema is implemented on a target IoT network, utilising in XC7A100T-FPGA as IoT nodes. Furthermore, both the conventional and the proposed RSA-2048 have been implemented in Spartan6-LX75 on a SAKURA-GW board. The results show that the proposed method has reduced the RSA execution time and consumption power of IoTD at about 50 and 60%, respectively. The most noticeable drawback of the current implementation is an overhead in the range of 30-53% on block-random access memory (RAM) usage.

RSA-CRT is one of the most common algorithms in the digital signature. Several side-channel attacks have been presented on the implementation of RSA-CRT. One of the most important side-channel attacks on RSA-CRT is Modular Reduction on Equidistant Data (MRED). The implementation of RSA-CRT has too many challenges in the multiplications when the key size is too long (e.g. 2048 bits). Montgomery multiplication is one of the common methods for executing the RSA multiplication, which has many implementation problems and side-channel leakage challenges. This article first implements an RSA-CRT algorithm based on the Montgomery multiplication with the high-speed and low area hardware. The implementation is named RSA-CRT-MMB (Montgomery Method Based). Next, a new power analysis side-channel attack on RSA-CRT-MMB is presented. We name our attack MRED on MMB. The attack utilizes new side-channel leakage information about the CRT reduction algorithm implemented by the MMB, for the first time. The previous articles do not investigate the MRED attack on Montgomery multiplication in RSA-CRT. Finally, a new countermeasure is presented to prevent the MREDM attack. The countermeasure does not have any overload in the hardware area or running time of the RSA algorithm. The correctness of our scheme, the 2048-bit RSA-CRT-MMB, is investigated by the implementation of the scheme on the SASEBO-W board in our DPA laboratory. The total running time of 2048-bit RSA is 250[Formula: see text]ms and the RSA algorithm occupies only 23% of LUT slice on Spartan-6 FPGA. The proposed countermeasures are also verified by practical experiments.

One of the most common algorithms in a digital signature is the RSA-CRT. Several side channel attacks have been presented on the RSA-CRT’s embedded design. Such attacks are divided into two categories: attack in the modular reduction step and attack in the recombination step. The former are plaintext attacks and based on the modular reduction on equidistant data attack, which is introduced in [B. den Boer, et al., “A DPA attack against the modular reduction within a CRT implementation of RSA,” in CHES 2002]. In these attacks, instead of using random plaintext, an equidistant series of input data is used. In a chosen and equidistant plaintext attack, the attacker needs a higher level of accessibility, and it is more difficult than a nonchosen plaintext attack. In this paper, we present a nonequidistant plaintext (but chosen plaintext) differential power analysis attack on the modular reduction in RSA-CRT, named NEMR (nonequidistant plaintext on modular reduction). We also present a new countermeasure on NEMR attack, which is resistant against equidistant and nonequidistant data attack on reduction step in RSA-CRT. In order to prove the idea, the NEMR attack is applied on the RSA-CRT 2048-bit implementation on SAKURA-G board, and the result is evaluated. Then, the presented countermeasure on NEMR attack is tested, and practical results demonstrate the validity of the proposed approach.