Abstract-In this paper an offset cancellation technique based on body voltage trimming is presented to be used in the comparators employed in Flash or Successive-Approximation analog-to-digital converters. The proposed offset cancellation is achieved by body voltage adjustment using low-power simple analog control feedback circuit without any additional capacitive loading at the comparator output. The accuracy of the proposed technique is higher than its digital calibration counterparts due to its analog nature. The technique is employed in the design of a 6-bit 1-GSps Flash ADC in 0.18μm CMOS technology. Simulation results show that using the proposed technique the standard deviation of the comparator offset is significantly reduced from 28mV to 750μV operating at 1-GHz with only 25μW power in offset cancellation. The cancellation scheme generally improves the ENOB by approximately 0.5 bit after cancellation.

In this paper an offset cancellation technique based on body voltage trimming is presented to be used in the comparators employed in Flash or Successive-Approximation analog-to-digital converters. The proposed offset cancellation is achieved by body voltage adjustment using low-power simple analog control feedback circuit without any additional capacitive loading at the comparator output. The accuracy of the proposed technique is higher than its digital calibration counterparts due to its analog nature. The technique is employed in the design of a 6-bit 1-GSps Flash ADC in 0.18μm CMOS technology. Simulation results show that using the proposed technique the standard deviation of the comparator offset is significantly reduced from 28mV to 750μV operating at 1-GHz with only 25μW power in offset cancellation. The cancellation scheme generally improves the ENOB by approximately 0.5 bit after cancellation.

No abstract

Flash Analog-to-Digital Converters (ADCs) are usually used in high-speed yet low-resolution applications such as wide band radio transceivers. Since the power consumption of such ADCs exponentially ri�es with the number of bits, low-power design techniques are of increasing interest. In this work, the power consumption of the comparators, the most important building blocks in such ADCs, have been reduced. First, a modified circuit configuration is proposed where the value of the kick-back noise is remarkably reduced. Then in order to save power, a power reduction technique is presented based on the principle of turning off the preamplifier of the comparators after the time when output voltages have been decided using an XOR gate. Since the difference of the input voltage with the reference level is not very small for most of the comparators in a Flash ADC, most of the comparators' outputs are ready before the end of the clock period and thus the proposed idea can save up to 40% of the power consumption of the entire ADC. In order to illustrate the effectiveness of the suggested idea, a 6-bit IGS/s ADC is designed and simulated in a 0.18/lm CMOS technology. The circuit consumes 20.2 m W from a 1.8-V supply voltage, and the THD is-32 dB at the input frequency of 200 MHz.