Three-dimensional integrated circuits (3DICs) have the potential to reduce interconnect lengths and improve digital system performance. However, heat removal is more difficult in 3DICs, and the higher temperatures increase delay and leakage power, potentially negating the performance improvement. Thermal vias can help to remove heat, but they create routing congestion, which also leads to longer interconnects. It is therefore very difficult to tell whether or not a particular system may benefit from 3D integration. In order to help understand this trade-off, physical design experiments were performed on a low-power and a high-performance design in an existing 3DIC technology. Each design was partitioned and routed with varying numbers of tiers and thermal-via densities. A thermal-analysis methodology is developed to predict the final performance. Results show that the lowest energy per operation and delay are achieved with 4 or 5 tiers. These results show a reduction in energy and delay of up to 27% and 20% compared to a traditional 2DIC approach. In addition, it is shown that thermal-vias offer no performance benefit for the low-power system and only marginal benefit for the high-performance system.

No abstract

Compact electrothermal modeling of lumped electrical devices and compact thermal modeling of volumetric materials enables efficient electrothermal modeling of microwave circuits. The compact thermal model of the body of an X-band MMIC is based on analytical solutions of the heat diffusion equation in thermal sub-volumes. The model is accurate and captures thermal nonlinearities. The model considers complex MMIC features such as surface metallization and vias, as well as the mounting configurations including lead-frame, carrier, and printed circuit board. This is coupled with electrothermal models of transistors and of resistors. The models are incorporated in a multi-physics simulator that uses the same model in both transient and harmonic analysis of an X-band LNA MMIC. Simulations are validated with steady-state thermal measurements.

No abstract

This work discusses a three dimensional network on chip (3D NoC) fabricated in the 0.18μm MIT Lincoln Laboratories 3D FDSOI 1.5V process. As a proof of concept, a three tier, 27 node, NoC test chip occupying 4 mm 2 per tier was designed and tested. It is the first of its kind to demonstrate successful inter-tier signaling in a complex three dimensional design, and validates the technology as a viable alternative to the continued scaling of conventional CMOS processes. Simulated results show that when implemented in this 3D process, simple 3D mesh interconnection networks allow for the sharing of global routing resources for complex systems while consuming an extremely low 2 mW of power per transaction. Using these results, we establish the need for a 3D network simulator to quantify the advantage 3D circuit implementations have over 2D.