Hybrid precoders, consisting of an analog hardware-constrained part operating at radio frequency (RF) and a digital part operating at baseband, reduce the RF implementation complexity and power consumption of multi-antenna transceivers, at the expense of some rate loss compared to an all-digital precoder. The analog and digital parts of the hybrid precoder are commonly designed by performing a constrained matrix decomposition (MD) of the all-digital precoder, which aims to minimize the Euclidean distance between the matrices corresponding to the hybrid and the all-digital precoder. In contrast, in this contribution we determine the zero-forcing (ZF) hybrid precoder that directly maximizes the weighted sumrate of a MU-MISO-OFDM communication system, taking into account various hardware constraints on the analog part. The resulting maximum rate serves as a useful benchmark for comparison with other ZF hybrid precoders. In a multi-carrier massive MIMO scenario, the rate-maximizing ZF precoders show a considerable performance advantage over MD-type hybrid precoders, indicating that the latter precoders are far from optimum. This contribution also investigates the trade-off between performance and computational complexity. Because of the iterative nature of the rate-maximizing ZF hybrid precoders, their superior performance comes with a large computational complexity. When this complexity cannot be afforded, one should revert to the MD-type precoders, at the expense of a considerable performance penalty; among the MD-type precoders, the non-iterative ones have only a slightly worse performance but a significantly smaller computational complexity, in comparison with the iterative ones.

In downstream spatial multiplexing involving multicarrier modulation using a hybrid precoder, several trade-offs have to be made with respect to the hardware complexity of the analog part of the precoder, the computational complexity of the precoders, and the performance of the communication system. Here, A class of hybrid precoding algorithms with reduced computational complexity is presented, that can be used under various hardware constraints. Our numerical results demonstrate that the proposed precoders allow one to trade off complexity against performance.

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