Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the process flow and ultimately quantifying its physical and electrical properties are critical steps in yielding mature technology. The standard build, test, and wait model of technology development is a major contributor to time and cost overruns. The growing inability to characterize many of the subtle and complicated features and yield limiting factors of a given technology is another serious constraint. We demonstrate the use of process modeling, virtual wafer fabrication, and virtual metrology in process development of advanced logic and memory. Accurate and predictive process modeling, in combination with virtual metrology enables the characterization of any feature on any given structure, is becoming a key requirement in advanced technology development. Virtual fabrication also accelerates the semiconductor development cycle, by substituting limited and lengthy wafer-based experiments with fast, large-scale virtual design of experiment. Several applications of virtual process modeling and metrology are illustrated in 3D NAND, DRAM, and logic technology. These applications include studies of 3D NAND pillar etch alignment (including tilt, twist, and bowing), DRAM capacitor process window optimization, advanced FinFET logic pitch-walking, and BEOL performance optimization.

In this work, the authors have investigated the dependence of the anisotropy level in an atomic layer etching (ALE) process of Al2O3 on form factor constraints when the ALE process involves etching in non-line-of-sight locations beneath a silicon nitride mask. In the experiments described here, thermal etching of Al2O3 without the use of any direction-inducing plasma components was explored utilizing the well characterized hydrogen fluoride/dimethyl-aluminum-chloride atomic layer etching process. The degree of anisotropy was quantified by measuring the ratio of lateral etch rate of this process in comparison to the vertical etch rate as a function of process step time inside 60 nm holes of aluminum oxide. Inside these holes, the authors determined that the horizontal etch rates slowed to an amount of 19% compared to the vertical rate when short process times were used. For process times operating in the saturation mode of the ALE process, horizontal etch rates per cycle could be sped up to 71% of the vertical rate but never reached parity with the latter. The authors propose a simple mechanism for explaining the anisotropy dependence on process step time and applied a reduced-order algorithm to model it. In this model, the authors introduced fitting parameters for surface modification depths and reaction times to match the experimentally found etch results. Conclusions could be drawn regarding topological hindrance or tortuosity for reactants to reach surfaces in shaded areas under the mask and for reaction by-products to escape from these locations and the impact on etch rate. In addition, the authors recognize that this mechanism could explain the unwanted depth dependence of the etch rate per cycle in high aspect ratio structures.