Phase-change random access memory (PRAM) is considered as one of the most promising candidates for future memories because of its good scalability and cost-effectiveness [1]. Besides implementations with standard interfaces like NOR flash or LPDDR2-NVM, application-oriented approaches using PRAM as main-memory or storage-class memory have been researched [2][3]. These studies suggest that noticeable merits can be achieved by using PRAM in improving power consumption, system cost, etc. However, relatively low chip density and insufficient write bandwidth of PRAMs are obstacles to better system performance. In this paper, we present an 8Gb PRAM with 40MB/s write bandwidth featuring 8Mb sub-array core architecture with 20nm diode-switched PRAM cells [4]. When an external high voltage is applied, the write bandwidth can be extended as high as 133MB/s.

This tutorial overviews flash memory solid-state drive technologies and recent advances in the field.

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The timing margin of an operating physical device suffers from crosstalk, power supply voltage fluctuation, and temperature variation among other elements. This problem is increasingly pronounced with deep-submicron technology. A conservative testing, binning and marketing policy alleviates the reliability concerns but at a loss of realizable performance of the device. This paper presents a methodology for a more practical estimation of the timing margin through analytical and empirical analysis of noise sources. First, the sources of noise are modeled. Then physical experiments are conducted to measure time-to-failure of the target CPUs under stress. The accelerated test results are used for parameterizing the models to empirically determine the device timing margin under realistic operating conditions. The results indicate that the actual safe-operating region for a set of tested microprocessors is significantly wider than that reported in manufacturer's' specifications for new devices.