Summary Musical instrument classification becomes effective when the music signal arrives with profound characteristics. This urged the researchers to develop an automatic system of recognizing the music signals and classify the instruments interplayed through the music. Thus, this paper proposes a model for the Indian music classification system using the optimization‐based stacked autoencoder. The significance of this research is based on the proposed Cuckoo‐dragonfly optimization (CuDro)‐based stacked autoencoder, where the proposed CuDro optimization trains the stacked autoencoder for acquiring accurate classification results. The proposed CuDro technique is the combination of the standard Cuckoo search (CS) and the Dragonfly algorithm (DA) that renders optimal weights for training the stacked autoencoder (SAE). Moreover, the musical instrument classification using the proposed CuDro‐based stack autoencoder is based on the compact features, such as Timbral features and proposed FrMkMFCC features, which further add value to this research. The Timbral features like Spectral flux, spectral kurtosis (SK), Spectral skewness, Spectral pitch similarity, Roughness, In harmonicity are added in the research for efficient musical instrument classification. The proposed FrMkMFCC feature is the integration of the Fractional Fourier transforms and Multi kernel method, and Mel Frequency Cepstral Coefficient (MFCC) features. The analysis using the developed classification methodology confirms that the proposed method acquired the maximum accuracy of 96.16%, the sensitivity of 86.86%, and specificity of 92.85%, respectively.

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Advanced Digital multipliers are the most critical arithmetic functional units. The general execution of these systems depends on the throughput of the multiplier. While negative bias temperature instability (NBTI) effects on logic gates are of major concern for the reliability of digital circuits, they become even more critical when considering the components for which even minimal parametric variations affect the lifetime of the overall circuit. In the mean time, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (V gs=−Vdd), increasing the threshold voltage of the pMOS transistor, and decresing multiplier speed. A similar phenomenon, positive bias temperature instability, happens when an nMOS transistor is under positive bias. Both effects or impacts reduce transistor speed, and in the long term, the system may fail because of timing infringement. Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier can give higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect.Keywords: Adaptive hold logic (AHL), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), reliable multiplier, variable latency.