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A distributed framework for logic simulation is presented. Switch-level simulation has been mapped to a distributed platform using a network of workstations on an Ethernet bus. Model parallelism is used with preprocessing to partition the circuit to be simulated among the processors. The simulation algorithm is decoupled from the communication layers to ensure easy portability. We have proposed a high level pipelining scheme with multiple buffers to overcome the effects of a low bandwidth network. Speedups of up to 4.1 with 5 processors have been obtained for medium sized ISCAS benchmark circuits. The speedups achieved using distributed simulation are very close to that obtained by the same switch-level simulator implemented on a shared memory parallel machine. Novel techniques to improve the performance of distributed simulation have also been implemented on a shared memory parallel machine.

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This paper presents performance comparison of lossless compression technique based on wavelets with progressive transmission capacity. Compressed images are used in various applications, where a large database has to be maintained. To store and retrieve such a large database lossless compression is essential. The performance achieved by this scheme is better than the Set Partitioning in Hierarchical Trees (SPIHT). The work also consists of comparative performances of various lossless and lossy compression techniques with progressive transmission capabilities. Compression ratio of 90 to 95% is achieved by this scheme.