This paper employs the concept of epistemic justice to examine the potential for gender equality plans (GEPs) to bring about sustainable transformative change towards gender equality in higher education. Mindful of both the limitations and opportunities of gender policy interventions, the paper highlights the importance of approaching gender inequality as a problem of justice and power rather than as an issue of “loss of talent.” The paper draws on Fricker's account of epistemic justice as well as on Bourdieu's analysis of power in the academic field, to evaluate seven GEPs in European universities for their potential to transform gender–power relations in academia. The analysis reveals that insufficient attention is paid to the role of academic power in creating gender injustice at all institutional levels and to the role of organizational culture in the perpetuation of gender inequalities in those settings. The study suggests that the incorporation of an epistemic justice lens in the creation of GEPs would address gendered power relationships and lead to sustainable equitable outcomes.

This paper is focused on the description of the physical layer of a new acoustic modem called ITACA. The modem architecture includes as a major novelty an ultra-low power asynchronous wake-up system implementation for underwater acoustic transmission that is based on a low-cost off-the-shelf RFID peripheral integrated circuit. This feature enables a reduced power dissipation of 10 μW in stand-by mode and registers very low power values during reception and transmission. The modem also incorporates clear channel assessment (CCA) to support CSMA-based medium access control (MAC) layer protocols. The design is part of a compact platform for a long-life short/medium range underwater wireless sensor network.

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1  Abstract-Deep submicron devices are expected to be increasingly sensitive to physical faults. For this reason, faulttolerance mechanisms are more and more required in VLSI circuits. So, validating their dependability is a prior concern in the design process. Fault injection techniques based on the use of hardware description languages offer important advantages with regard to other techniques. Firstly, as this type of techniques can be applied during the design phase of the system, they permit reducing the time-to-market. Secondly, they present high controllability and reachability. Among the different techniques, those based on the use of saboteurs and mutants are especially attractive due to their high fault modeling capability. However, implementing automatically these techniques in a fault injection tool is difficult. Especially complex are the insertion of saboteurs and the generation of mutants. In this paper we present new proposals to implement saboteurs and mutants for models in VHDL which are easy-to-automate, and whose philosophy can be generalized to other hardware description languages.Index Terms-Logic design, very large scale integration, physical faults, fault tolerance, dependability validation, hardware description languages, VHDL-based fault injection, saboteurs, mutants.

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