We study the hysteresis in threshold voltage shift during alternating gate bias ramps ͑drain current vs gate voltage ͑IdVg͒ sweeps͒ after negative bias temperature stress and compare the results with carefully recorded charge pumping measurements. This allows us to clearly identify three different types of defects. All defect types have in common that their charge state depends on the position of the Fermi level and that they introduce a broad density of states ͑DOS͒ in the vicinity or within of the silicon band gap. Defect I is fully recoverable, defect II is similar to defect I in terms of DOS but does not recover, while defect III can be attributed to the conventional interface states. With a precise microstructural model in mind, and by using specific test chips, which allow us to vary stress bias and temperature quasiarbitrarily, we come to the conclusion that the carrier trapping and detrapping characteristics of stress induced defects can be controlled by temperature and electric field in a similar way, but that irrevocable structural relaxation is mainly influenced by temperature. Based on these ideas, we present a measurement method which can be used to energetically profile the relaxation of stress induced oxide defects.

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Reliability stress testing of power semiconductors requires significant development effort for a test apparatus to provide the required functionality. This paper presents a modular test system architecture which focuses on flexibility, reusability and adaptability to future test requirements. Different types of tests for different devices in application circuit configuration can be implemented based on the same modular test system concept. Vital parameters of the device under test (DUT) can be acquired in situ during the running stress test. This enables to collect drift data of this parameters. The control and data acquisition parts of the test system are separated from the actual test circuit. With this physical separation, the same control part can be used for different types of tests. Experimental results of a prototype test system are provided.