In this article, basic irreversible gate (XOR gate) and basic reversible gates are designed using dataflow design. The output of all the basic gates are simulated and compared the power in Analyze power (Xpower) compiler. The combinational circuits (adder and subtractor) and sequential circuit (T flip flop) are designed using structural design with both conventional logic gates and reversible logic gates and power has been measured. Overall the power of conventional logic gates and reversible logic gates are compared that helps us to design gates with less power dissipation and more efficiency. All the individual reversible logic gates and complex combinational and sequential circuits are described in VHDL hardware description language and this circuits are functionally verified using Xilinx ISE 9.1i (student version) software.