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1NTRODUCTIONHafnium-based high-K dielectrics such as HfOz, HfON and HfSiON have attracted a great deal of attention because of their potential for successful integration into CMOS technology. However, channel mobility degradation, charge trapping and reliability are major concerns. In this paper, we will review our recent research results, namely, the charge trapping characteristics, the effects of nitrogen on minority carrier lifetime and channel mobility, and Hf-Ti-0 dielectrics. We have investigated how N affects the minority carrier lifetime in the Si substrate and how it relates to pcff. A new dielectric stack consists of TrOz/HfOz bilayer has shown improved thermal stability and increased K value (thus scaled EOT < I.0nm) without the disadvantages of incorporated N. EXPERIMENTALMOSCAPs and MOSFETs (both n-channel and p-channel) with Hf02, HfO,N,, and HfSiON gate dielectrics deposited using PVD or ALD methods; and TaN, TiN or polysilicon gate electrodes have been fabricated (the detailed fabrication process can be found in [l-61). Also a bi-layer structure of TiOJHfOz multi-metal dielectrics have been formed by DC magnetron sputtering of hafnium and titanium targets in Ar ambient (more details are given below). Most of these dielectrics have undergone a post-deposition anneal (PDA) at -5OO'C immediately after the dielectric deposition; and a PMA (post-metal anneal ranging from 600-900T). RESULTSA recent approach to achieve top nitridation of high-k dielectrics was via HfO,N, on the top of high-k dielectrics [7]. The application of HfON on top of HfOz was effective in suppressing the diffusion of both oxygen and dopant. But it was found that the incorporated N amount was so limited. In this work, HfSiON was applied on HfOz to achieve higher N concentration at the top of dielectrics while keeping higher mobility. The effects of top nitridation on MOSFET performance of high-k devices have been investigated. For the HfSiONiHfO? ("top silicon and nitrogen": Fig. 1) gate stack, a very thin HfSiON (-8 A) layer was formed on the top of HfOz (35-40 A) by co-sputtering Hf and Si in Ar/N2/02 ambient. For higher dielectric constant, the ratio of HfiSi was kept larger than 1 in the HfSiON process. This was followed by rapid-thermal annealing at 550-600°C in Nz for 20 sec. The MOS capacitors and N-MOSFETS were fabricated with TaN (-200 nm) gate electrodes by reactive sputtering. Conventional self-aligned process was used for transistors and deuterium annealing at 6OOoC for 20 min was done before AI metal deposition for better transistor performance. In short, this TSN ("Top-Silicon-Nitrogen" dielectrics ( Fig. 1)) is designed to put N near the top of the HfOz structure so that it can incorporate more N (because Si "traps" N and prevents N out-diffusion) and keeps the N away from the Si interface (N at the SI interface can degrade channel mobility).The Zerbst plots for various HfOz and nitrogen-incorporated HfOz MOSCAP are shown in Fig. 2, It shows that TaN gate devices resulted in reduced minority carrier lifetime in the ...

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