Koiran [8] showed that if an n-variate polynomial fn of degree d (with d = n O(1) ) is computed by a circuit of size s, then it is also computed by a homogeneous circuit of depth four and of size 2 O( √ d log(n) log(s)) . Using this result, Gupta, Kamath, Kayal and Saptharishi [7] found an upper bound for the size of a depth three circuit computing fn. We improve here Koiran's bound. Indeed, we show that it is possible to transform an arithmetic circuit into a depth four circuit of size 2 O √ d log(ds) log(n) . Then, mimicking the proof in [7], it also implies an 2 O √ d log(ds) log(n)upper bound for depth three circuits. This new bound is not far from optimal in the sense that Gupta, Kamath, Kayal and Saptharishi [6] also showed a 2 Ω( √ d) lower bound for the size of homogeneous depth four circuits such that gates at the bottom have fan-in at most √ d. Finally, we show that this last lower bound also holds if the fan-in is at least √ d.

An Algebraic Circuit for a polynomial P P Frx 1 , . . . , x N s is a computational model for constructing the polynomial P using only additions and multiplications. It is a syntactic model of computation, as opposed to the Boolean Circuit model, and hence lower bounds for this model are widely expected to be easier to prove than lower bounds for Boolean circuits.

The Simplex Tree (ST) is a recently introduced data structure that can represent abstract simplicial complexes of any dimension and allows efficient implementation of a large range of basic operations on simplicial complexes. In this paper, we show how to optimally compress the Simplex Tree while retaining its functionalities. In addition, we propose two new data structures called the Maximal Simplex Tree (MxST) and the Simplex Array List (SAL). We analyze the compressed Simplex Tree, the Maximal Simplex Tree, and the Simplex Array List under various settings.

Abstract. Koiran [8] showed that if an n-variate polynomial fn of degree d (with d = n O(1) ) is computed by a circuit of size s, then it is also computed by a homogeneous circuit of depth four and of size 2. Using this result, Gupta, Kamath, Kayal and Saptharishi [7] found an upper bound for the size of a depth three circuit computing fn. We improve here Koiran's bound. Indeed, we show that it is possible to transform an arithmetic circuit into a depth four circuit of size. Then, mimicking the proof in [7], it also impliesupper bound for depth three circuits. This new bound is not far from optimal in the sense that Gupta, Kamath, Kayal and Saptharishi [6] also showed a 2 Ω( √ d) lower bound for the size of homogeneous depth four circuits such that gates at the bottom have fan-in at most √ d. Finally, we show that this last lower bound also holds if the fan-in is at least √ d.