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In a multi-channel radiation detector readout system, waveform sampling, digitization, and raw data transmission to the data acquisition system constitute a conventional processing chain. The deposited energy on the sensor is estimated by extracting peak amplitudes, area under pulse envelopes from the raw data, and starting times of signals or time of arrivals. However, such quantities can be estimated using machine learning algorithms on the front-end Application-Specific Integrated Circuits (ASICs), often termed as “edge computing”. Edge computation offers enormous benefits, especially when the analytical forms are not fully known or the registered waveform suffers from noise and imperfections of practical implementations. In this work, we aim to predict peak amplitude from a single waveform snippet whose rising and falling edges containing only 3 to 4 samples. We thoroughly studied two well-accepted neural network algorithms, Multi-Layer Perceptron (MLP) and Convolutional Neural Network (CNN) by varying their model sizes. To better fit front-end electronics, neural network model reduction techniques, such as network pruning methods and variable-bit quantization approaches, were also studied. By combining pruning and quantization, our best performing model has the size of 1.5 KB, reduced from 16.6 KB of its full model counterpart. It can reach mean absolute error of 0.034 comparing to that of a naive baseline of 0.135. Such parameter-efficient and predictive neural network models established feasibility and practicality of their deployment on front-end ASICs.

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This paper discusses a large number of logic circuit mapping methods for complex systems, focusing on network hardware system designs. This logic mapping technique enables significant logic simulation time savings by mapping identical logic processor modules. Under the logic mapping method which is called the time division multiplexing (TDM) logic mapping method, the speed of the required to simulate it is significantly reduced, compared with conventional mapping methods, when folding the identical modules into a single module copy is done at the hardware description language (HDL) level. In principle, this method can be applied to any type of a network design platform, e.g., communication data stream through physical channel (fiber optic line), video signal transfer logic display environment, etc. In this paper, we demonstrate this method using several configurations of the IBM Serial Link architecture.

We investigated that the brightness magnitude of the Del Cephei had been adapted to three different training values and each training had four different hidden layers in the back-propagation neural network (BPNN) models. The best forecasting mean through different approaches in the BPNN model was obtained at 15% training with four hidden layers. However, the difference in forecasting accuracies of the different levels was not statistically significant.