Amorphous silicon (a-Si) films were crystallized using three grain growth modes induced by micro-thermal-plasma-jet (µ-TPJ) irradiation and applied to the channel regions of thin-film transistors (TFTs). Solid phase crystallization (SPC) formed microcrystalline grains and showed a lower crystallinity of 70%, whereas leading wave crystallization (LWC) and high-speed lateral crystallization (HSLC) formed significantly larger grains than the TFT channel region. The SPC-TFT showed a lower field-effect mobility (μFE) due to the small grain size and the existence of many grain boundaries, whereas LWC- and HSLC-TFT channels were formed by only single grains and showed a μFE higher than 300 cm2 V−1 s−1 in the n-channel. The defect density of HSLC was smaller than that of LWC; consequently, the HSLC-TFT performed better than the LWC-TFT. The maximum μFE values of n- and p-channel HSLC-TFTs were 418 and 224 cm2 V−1 s−1, respectively.

No abstract

A novel layer transfer and simultaneous crystallization of amorphous silicon (a-Si) films induced by near-infrared semiconductor-diode-laser (SDL) irradiation has been investigated. The a-Si films supported by narrow quartz columns on a starting quartz substrate and a counter substrate [glass and poly(ethylene terephthalate)] were in face-to-face contact, and an SDL irradiated the a-Si films with midair structure. After SDL irradiation, the Si films were completely transferred and crystallized simultaneously on the counter substrates. In-situ monitoring revealed that the layer transfer took place either in the solid phase or the liquid phase followed by phase transformation in the cooling period. High performance polycrystalline Si thin-film transistors were successfully fabricated on the transferred Si films, which showed a high on/off ratio of more than 105 and a field-effect mobility as high as 268 cm2 V-1 s-1.

High performance thin film transistors (TFTs) are fabricated on quarts substrate based on zone-melting-recrystallization (ZMR) of amorphous silicon (a-Si) strips induced by micro-thermal-plasmajet (µ-TPJ) irradiation. The grain boundaries (GBs) in strip pattern were almost excluded and most of the strips consist of ∑3 coincidence site lattices (CSLs) or in some cases single grains. Strip pattern was quite effective even in the case of short channel TFTs. N-and p-channel TFTs with typical field effect mobility (µ FE ) of 380 and 140 cm 2 /Vs, respectively, are successfully fabricated with significantly reduced characteristics variability. These high µ FE and low variation of threshold voltage (V th ) by strip pattern showed significantly stable output characteristics regardless of the size of TFTs.

The crack generation mechanism and the effect of crack reduction by buffer SiO 2 layer insertion in thermal-plasma-jet (TPJ) crystallization of an amorphous silicon film on a glass substrate have been investigated. The crack generation was clearly observed 13.7 s after TPJ irradiation using a high-speed camera, which indicates that cracks are generated not during heating, but during cooling. From the measurement and simulation of substrate deformations, it was clarified that the substrate deformed convexly during heating and it consequently deformed concavely after cooling owing to the substrate surface densification. This result indicated that the tensile stress generated by the concave deformation is the origin of cracks. The deposition of the buffer SiO 2 layer generated compressive stress, which minimizes accumulation of tensile stress after TPJ annealing. The number of cracks in unit length significantly decreased owing to the decrease in tensile stress with the increase in the thickness of the buffer SiO 2 layer.