This paper presents a 14‐Gb/s dual‐mode receiver with MIPI D‐PHY and C‐PHY interfaces for mobile display drivers. To reduce size overhead from the dual‐mode interfaces, we propose the termination circuit that shares 50‐Ω terminations and common‐mode capacitors while maintaining a perfectly matched load balance. The proposed dual‐mode receiver can support 14‐Gb/s total bandwidth in each interface mode, resulting in broad compatibility with application processors. A mobile display driver using the proposed dual‐mode receiver is fabricated in a 28‐nm high‐voltage CMOS process and verified up to 3.5 Gb/s per lane in the D‐PHY mode and 2.2 Gs/s per trio in the C‐PHY.

This paper presents a timing controller embedded driver (TED) IC with 3.24‐Gbps embedded display port (eDP), which is implemented using a 45‐nm high‐voltage CMOS process for the chip‐on‐glass (COG) TFT‐LCD applications. The proposed TED‐IC employs the input offset calibration scheme, the zero‐adjustable equalizer, and the phase locked loop‐based bang‐bang clock and data recovery to enhance the maximum data rate. Also, the proposed TED‐IC provides efficient power management by supporting advanced link power management feature of eDP standard v1.4. Additionally, the smart charge sharing is proposed to reduce the dynamic power consumption of output buffers. Measured result demonstrates the maximum data rate of 3.24 Gbps from a 1.1 V supply voltage with a 7.9‐inch QXGA 60‐Hz COG‐LCD prototype panel and 44% power saving from the display system.

This paper presents a 14-Gb/s dual mode receiver with MIPI D-PHY and C-PHY interfaces for mobile display drivers. To reduce size overhead from the dual mode interfaces, we propose the termination circuit that can share 50-Ω terminations and common-mode capacitors while maintaining a perfectly matched load balance. The proposed dual mode receiver supports up to 14 Gb/s total bandwidth in each interface mode, resulting in broad compatibility with application processors. A mobile display driver using the proposed dual mode receiver is fabricated in a 28-nm high-voltage CMOS process and verified up to 3.5 Gb/s per lane in the D-PHY mode and 2.2-Gs/s per lane in the C-PHY.

This paper presents a timing controller (TCON) embedded driver (TED) IC with 3.24‐Gbps embedded display port (eDP) which is implemented using a 45nm high voltage CMOS process for the chip‐on‐glass (COG) TFT‐LCD applications. The proposed TED‐IC employs the input offset calibration scheme, the zero‐adjustable equalizer and the PLL based bang‐bang CDR to enhance the maximum data rate. Also the smart charge sharing (SCS) is proposed to reduce the dynamic power consumption of output buffers. Measured result demonstrates the maximum data rate of 3.24Gbps from a 1.1V supply voltage with a 7.9‐inch QXGA 60‐Hz COG‐LCD prototype panel and 44% power saving from the display system.