We have bias-stressed hydrogen-passivated polycrystalline silicon thin-film transistors by varying the bias condition and have measured the change in the field-effect conductance activation energy as a result of the bias stress. For stress by a high gate bias voltage, a slight broadening occurs in the activation energy curve, while stress by a low gate bias voltage gives rise to a shoulder. Numerical calculation shows that the change in activation energy is due to defect generation in the poly-Si layer and for stress by low gate voltage, defects are localized near the drain region. The energy distribution of defects cannot be obtained accurately, but its position is higher than 0.2 eV above midgap.