AiPi technology incorporates an embedded clock and control scheme with a point‐to‐point bus topology, achieving the smallest possible number of interface lines between a timing controller and source drivers. A point‐to‐point architecture enables the data rate to be boosted and the number of interface lines to be reduced because impedance matching can be easily achieved. An embedded clock and control scheme is implemented by means of multi‐level signaling resulting in simple clock/data recovery circuitry. A 46″ AiPi‐based 10‐bit FHD prototype requires only 20 interface lines, compared to 38 lines for mini‐LVDS. The measured maximum data rate per one data pair is more than 800Mbps.

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Recently, a single phase driving method has been adopted for driving CCFL lamps to provide a low cost implementation. However, high voltage driving signals are coupled to pixel electrodes through parasitic capacitance between the lamps and panel electrodes, generating artifacts in the display. This paper describes the analysis results of this phenomenon and the proposed automatic delay compensation scheme eliminates the artifacts caused by the coupling effect.

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