High Voltage Monolithic Active Pixel Sensors (HV-MAPS) are based on a commercial High Voltage CMOS process and collect charge by drift inside a reversely biased diode. HV-MAPS represent a promising technology for future pixel tracking detectors. Two recent developments are presented. The MuPix has a continuous readout and is being developed for the Mu3e experiment whereas the ATLASPix is being developed for LHC applications with a triggered readout. Both variants have a fully monolithic design including state machines, clock circuitries and serial drivers. Several prototypes and design variants were characterised in the lab and in testbeam campaigns to measure efficiencies, noise, time resolution and radiation tolerance. Results from recent MuPix and ATLASPix prototypes are presented and prospects for future improvements are discussed.

New active pixel detectors, based on the high-voltage CMOS technology, have been recently introduced into the HEP community. The design principle relies in the pixel electronics being integrated inside the silicon substrate itself. Applied to particle tracking detectors, major advantages of the HV-CMOS technology with respect to standard silicon detectors are very low material budget, fast charge collection time, high-radiation tolerance, operation at room temperature and low cost.Within the R&D for the future ATLAS tracker upgrade for the High-Luminosity LHC program, the HV2FEI4 is a HV-CMOS prototype chip developed in 180 nm AMS technology H18. It has been designed to be compatible with both a pixel and a strip readout ASIC. In this paper, first experience in operating the HV2FEI4 chip is reviewed. Preliminary results after neutron irradiation up to 10 16 n eq /cm 2 and after X-ray irradiation up to 100 Mrad are shown.

The inner tracker of the ATLAS detector will be replaced at the future upgrade to keep the performance at high luminosity operation. We have developed the super-module integration concept based on double-sided silicon strip modules. A super-module consists of twelve double-sided modules, each of these having 80 readout ASICs. Each chip has 128 readout channels, thus a total of 122880 channels per super-module. Since the number of readout strips becomes very large to keep the hit occupancy at an acceptable level, the data readout is one of the key issues. We have developed a readout system based on the Soi Evaluation BoArd with Sitcp (SEABAS). The SEABAS processes the data from the super-modules by means of an FPGA (User-FPGA) and transfers data to a computer via Ether-net with SiTCP protocol, a technology to realize direct access and transfer the data in the memory of the User-FPGA from the PC by utilizing TCP/IP and UDP communication with a dedicated FPGA. We developed the firmware and the software for the SEABAS, together with the readout hardware chain, and established basic functionality for reading out the super-module.