Wide-bandgap power devices have enabled singlephase totem-pole (TP) power factor correction (PFC) converter designs to be switched at several tens of kilohertz under hardswitching and hundreds of kilohertz under soft-switching. It is straightforward to analyze and compare the volume of boost inductor for TP PFC converters having multileg and multilevel configurations operating under continuous-conduction-mode (CCM) and critical-conduction-mode (CrM) at various switching frequencies; however, the impact of topology and switching frequency selections remains unchallenged for generated differential mode (DM) noise. This article proposes a unified and generalized DM noise estimation method for multileg, and multilevel TP PFC converters operated under both CCM and CrM operation modes. The method has been verified with simulation results obtained from various TP PFC topologies, as well as experimental results obtained from singleleg CCM and 4-Level CCM TP PFC converters. The empirically determined boxed sizes of DM filters have been compared among various TP PFC topologies, and the best switching frequency for each topology has been determined with the integration of boost inductor volume comparison.

LLC converter design optimization remains a challenging task for varying loads such as in battery chargers. There are numerous L-L-C combinations to choose from a design space that can satisfy the required voltage gains of the application. An accurate magnetic model is essential to optimally size the passive components according to the application needs. This paper provides a new design tool for gapped core magnetics to optimize the transformer and resonant inductor in LLC converters. Unlike conventional design algorithms, the proposed algorithm considers multiple distributed cores and selects the optimal magnetic flux density by minimizing a penalty function that includes power loss, cost and volume of the magnetic components using Big-Bang Big-Crunch Algorithm. The gapped core transformer and inductor design equations have been verified in Ansys Maxwell and Simplorer co-simulation environment for a 3700W 48V LLC and calculated power loss have been compared with experimental results. For the given L m and L r pair of 37.52 µH and 9.38 µH, the proposed magnetic model designed a transformer with twodistributed cores, each one exhibiting a magnetizing inductance of 17.73 µH and leakage inductance of 0.7 µH on a EE422120 with 3F36 material. The total power loss of the transformers are measured as 12.44 W on a 3700 W prototype switched at 350 kHz.INDEX TERMS Big-bang big-crunch algorithm, gapped core magnetics, light electric vehicle, LLC converter, LLC transformer optimization, multi-core LLC transformer.

Latest developments in low voltage wide-bandgap semiconductor technology have increased the popularity of single-phase multi-level (ML) totem pole (TP) power-factor correction (PFC) converters. Phase shifted flying capacitor based power stages offer several advantages, such as higher input current ripple frequency, smaller size inductor and differential mode (DM) filter, and usage of low voltage Gallium Nitride (GaN) devices with better figure-of-merit. Even though it has been proven that ML TP PFC converters have good power density and efficiency, the determination of optimal voltage levels and switching frequency requires a system-level optimization. This paper proposes an optimization framework for ML TP PFC converters, taking the power stage, thermal, DM filter, and magnetic designs, as well as practical design considerations, into account to determine the voltage-levels and switching frequency that minimize the power losses, cost and volume of the total system. To process output power of 3700W, the optimization tool suggests using a 4-Level GaN TP PFC topology switched at 45 kHz. The outcome of the tool has been compared with other fixed inductor current ripple designs, as well as optimized designs for 3-Level and 5-Level TP PFC converters in terms of cost, volume, and power losses. In accordance with the optimization results, a prototype of a 4L TP PFC rated at 3700 W is designed, which achieves a peak efficiency of 99.6% at 1 kW and >99.1% efficiency under the full power range.INDEX TERMS Ac/dc conversion, multi-level, optimization, power factor correction, totem-pole.

LLC rezonans dönüştürücü tasarımı, Lm, Lr, Cr ve kalite faktörünün gerilim kazancının karmaşık bir fonksiyonu olması ve uygulamaya bağlı olarak gerilim kazançlarını kapsayan Sıfır Gerilimde Anahtarlama’yı (SGA) sağlayabilecek anahtarlama frekansı aralığı seçiminin zorluğundan dolayı elektrikli araç şarj uygulamaları için hayli zorlu bir tasarım problemidir. Bu çalışma, hava aralıklı manyetik bileşenler için birden fazla tasarım bileşenini ve kısıtını bir arada değerlendirebilen, doğadan esinlenen matematiksel yöntem tabanlı yeni bir tasarım yöntemi sunmaktadır. Önerilen yeni yöntem Parçacık Sürüsü Algoritması ile, oluşturulan çekirdek veri tabanındaki birçok çekirdek arasından en uygun tasarımı seçmektedir. Geleneksel tasarım algoritmalarından farklı olarak önerilen algoritma, manyetik bileşenlerin kaybını, maliyetini ve hacmini içeren bir amaç fonksiyonunu en aza indirerek en uygun manyetik akı yoğunluğunu belirlemektedir. Sunulan yöntem hafif bir elektrikli araç şarj cihazındaki 3700W, 48V LLC rezonans dönüştürücü için denenmiştir. Algoritma içinde birincil ve ikincil sargılarda sırasıyla seri ve paralel çoklu bağlamaların uygulandığı çok çekirdekli yapılar dikkate alınarak bir tasarım çalışması yapılmıştır. Tasarlanan manyetik bileşenler Ansys Electronic Desktop ve Simplorer ortak benzetim ortamında doğrulanmış ve çekirdek veri tabanından en uygun çekirdek yapıları seçilmiştir. Önerilen yöntemin en uygun LLC rezonans dönüştürücü tasarımını bulmak için çoklu kombinasyonların bir arada ve hızla değerlendirilebileceği sistem düzeyinde bir optimizasyon algoritmasının bir parçası olarak kullanılabileceği görülmüştür.

GaN FET switches have opened new horizons in power electronics converters due to their small package size and their ability to provide high operating voltage-current values at higher switching frequencies. This study presents the finite element method (FEM) based thermal model of EPC2215 (VDS=200V, ID=32A, RDS(on)=8m) GaN FET switches produced by EPC company in small package sizes. Firstly, the test procedures determined by the JEDEC standards have been applied to the established FEM-based model. The thermal resistances of the switch from junction to case, junction to ambient, and junction to board have all been estimated using the FEM-based simulation model and compared with the thermal resistance values given in the datasheet. Afterwards, the thermal model of the EPC9099 half-bridge development board that uses EPC2215 switches has been developed. The power loss values given in the datasheet have been applied to the thermal model. As a result of the simulation, the regions where the development board was subjected to thermal stress were identified. Finally, the thermal map results obtained by the simulation have been compared with the thermal camera readings captured during experiments.