For the first time, by using 3-D TCAD, the advantage of using complementary FET (CFET), which has vertically stacked nanosheet nFET and pFET with shared gate, is compared to standard CMOS with nanosheet FETs in perspective of CMOS inverter performance. The comparative study on CMOS operation was performed between CFET and standard CMOS in 3-nm technology node. The results indicate that, when both devices have identical DC electrical characteristics, using CFET can increase the frequency by ~2.3% in iso-power and decrease power by ~7.3% in iso-frequency compared to the standard CMOS with separate n/pFETs while effectively reducing the area by ~55%. It is also investigated that such results are due to the approximately 4.5% low effective capacitance (Ceff) of the CFET compared to the standard CMOS. This low Ceff of CFET arises from the stacked structure, which causes the gate-fringe electric field overlap and short via pitch between nFET and pFET. Furthermore, the performance of CFET by different n/pFET separation distances, channel lengths, and widths are analyzed. This study can provide critical insight into the performance improvement by using CFET for sub 3-nm technology.

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For the first time, device design guidelines for a 3-nm node complementary field-effect transistor (CFET), which vertically stacks n-type and p-type nanosheet MOSFETs with a shared gate, are investigated using calibrated 3-D technology computer-aided design (TCAD). Here, the optimal device dimensions of the CFETs for better inverter performance and thermal characteristics are studied. The electrothermal performance are investigated for various vertical dimension parameters of CFET, such as the number of stacked channels, vertical distance between nanosheet channels (D nsh ), distance of n/pMOS separation (D n/p ), and channel thicknesses (T nsh ). The results show that, unlike conventional CMOS, the reduction of D nsh and D n/p of CFET can effectively improve inverter performance without severe thermal degradation, although other dimensional parameters trigger a severe trade-off between different electrothermal parameters. The reduction of D nsh and D n/p decreases C eff with a lower metal via the height and gate fringing effect. However, the reduction in D nsh and D n/p does not change R eff ; therefore, both the operation frequency (f ) and power-product delay (PDP) can be improved. In the case of thermal characteristics, the reduction of D nsh and D n/p slightly increases both T max and R th because of thermal coupling but is negligible. Therefore, the reduction of D nsh and D n/p will be a key technique for the development of sub-3-nm CFET.INDEX TERMS Complementary FET (CFET), nanosheet FET (NSHFET), technology computer-aided design (TCAD), 3-nm technology node.

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