A plastic chip that can perform immunoassays using an enzyme as signal generator, i.e., ELISA-on-a-chip, was developed by incorporating an immunostrip into channels etched on the surfaces of the chip. To utilize an analytical concept of cross-flow chromatography, the chip consisted of two cross-flow channels in the horizontal and vertical directions. In the vertical channel, we placed a 2-mm-wide immunostrip for cardiac troponin I (cTnI), which was identical to a conventional rapid test kit except for the utilization of an enzyme, horseradish peroxidase (HRP), as tracer. An enzyme substrate supply channel and a horizontal flow absorption pad compartment were transversely arranged on each lateral side of the signal generation pad of the strip, respectively. Upon application of a sample containing cTnI, it migrated vertically through the membrane strip by capillary action, and antigen-antibody binding occurred. After 15 min, the horizontal flow was initiated by the addition of a chromogenic substrate solution for HRP into the supply channel and by partial superimposition of the horizontal flow absorption pad onto the signal generation pad. A color signal proportional to the analyte concentration was produced on this pad, measured after 5 min as optical densities using a digital camera-based detector, and quantified by integration of the densities under the peak after normalization. Its calibration curve indicated that the detection limit of the chip was approximately 0.1 ng/mL and its quantification limit was 0.25 ng/mL. In measuring blindly prepared samples, the chip performance correlated with that of a reference system, Beckman Coulter Access, within 2.5-fold discrepancy at the detection limit.

Abstract-This paper proposes a 16x16 and 32x32 inverse transform architecture for HEVC (High Efficiency Video Coding). HEVC large transform of 16x16 and 32x32 suffers from huge computational complexity. To resolve this problem, we proposed a new large inverse transform architecture based on hardware reuse. The processing element is optimized by exploiting fully recursive and regular butterfly structure. To achieve low area, the processing element is implemented by shifters and adders without multiplier. Implementation of the proposed 2-D inverse transform architecture in 0.18 m technology shows about 300 MHz frequency and 287 Kgates area, which can process 4K (3840x2160)@ 30 fps image.

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