The authors present a low‐power area‐efficient subarray beamforming receiver (RX) structure for a miniaturized 3‐D ultrasound imaging system. Given that the delay‐and‐sum (DAS) and digitization functions consume most of the area and power in the receiver, the beamforming successive approximation register (SAR) analog‐to‐digital converter (ADC) shares its capacitive digital‐to‐analog converter (CDAC) with the delay cells. As a result, the delay cells implemented with capacitors are embedded in the CDAC with significant area reduction, further eliminating the need for power‐hungry ADC buffers. Furthermore, the dual reference 10‐bit SAR ADC reduces the area of CDAC by 32 times, achieving a switching energy reduction of 98.3%, compared to the conventional SAR ADC. As a result, the proposed beamforming SAR ADC, simulated using a 0.18 μm CMOS process, consumes 230 μW per channel, significantly reducing the per channel capacitance.

We present a 64-channel implantable neural stimulator with sub-nC charge balanced current stimulation for seizure suppression applications. The regulated cascode current driver achieves almost full VDD compliance voltage range. A passive charge balancing by shorting working and reference electrodes with a bootstrapped switch keeps the residual charge level within a safe limit, enabling faster-switching operation. The stimulation parameters, such as current pulse width, channel activation, activation frequency, and current amplitude, are highly reconfigurable and adjusted through the SPI interface. Significantly, the current amplitude can be varied from 1μA to 1.8 mA. As a result, the proposed neural stimulator fabricated with a 0.18μm standard CMOS process effectively suppresses seizures within a safe limit with a residual charge of less than 1nC through the in-vivo test.

We present a low-power area-efficient subarray beamforming receiver (RX) structure for a miniaturized 3-D ultrasound imaging system. Given that the delay-and-sum (DAS) and digitization functions consume most of the area and power in the receiver, the beamforming successive approximation register (SAR) analog-to-digital converter (ADC) shares its capacitive digital-to-analog converter (CDAC) with the delay cells. As a result, the delay cells implemented with capacitors are embedded in the CDAC with significant area reduction, further eliminating the need for power-hungry ADC buffers. Furthermore, the dual reference 10-bit SAR ADC reduces the area of CDAC by 32 times, achieving a switching energy reduction of 98.3%, compared to the conventional SAR ADC. As a result, the proposed beamforming SAR ADC, simulated using a 0.18 μm CMOS process, consumes 230 μW per channel, significantly reducing the per channel capacitance.