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To enhance the on-current (I ON) of a tunneling field-effect transistor (TFET), we investigated the structures of a TFET with a recessed active (RA) region, known as the “RA-TFET”, using three-dimensional (3D) simulation. The analyzed structure is different from the recessed dynamic random-access memory (DRAM) channel in terms of the positions of the source and drain. The benefit of this structure is that the tunneling length remains unchanged as the depth increases so that the current can be easily scaled up, thereby maintaining the subthreshold slope (SS) and active area. Using an RA-TFET with a 100 nm Si depth, a 9.45 × 10−7 A I ON is achieved with a minimum SS of 35 mV/dec; in addition, we propose RA-TFET modifications to mitigate the ambipolar characteristics and reduce the capacitance between the gate and the drain (C GD) by up to 40%.