A three-step tapered bit period asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is proposed to reduce the total DAC settling time by 47.7% compared to the non-tapered conversion time with less design overhead. Unlike conventional approaches, the SAR settling time analysis with both reference buffer output impedance and hardware overhead is first analyzed in each conversion step, which demonstrates that the three-step tapered bit period approach is the most time- and hardware efficient in our design. Additionally, area-efficient three-step clock generation is proposed by sharing resistors for delay generation, resulting in a small area increase of only 20.4% compared to the non-tapered clock generation. As a result, the proposed technique is used to reduce the reference buffer’s power and increase the sampling frequency. The maximum allowed output impedance of the reference buffer for SFDR > 92 dB becomes larger than that of the non-tapered design by 200 Ω, translated to a sampling frequency increase from 6 MHz to 8 MHz in our design. The proposed three-step tapered bit period using an area-efficient clock generator was designed in a 55 nm CMOS process. The clock generator occupies 0.00081 mm2 out of 1143 μm × 81 μm overall size. The power consumption of the 8 MS/s 12-bit SAR ADC with proposed clock generation is 128.91 μW when under 1 V supply.

This paper presents a fully-differential touch screen panel (TSP) self-capacitance sensing (SCS) system with a self-capacitance mismatch calibration technique. Due to the self-capacitance mismatch of TSP, the analog front-end (AFE) of the receiver (RX) circuit suffers from dynamic range degradation and gain limitations, which lead to the signal-to-noise ratio (SNR) loss for the TSP SCS system. The proposed calibration introduces the difference in input resistance and the driving amplifier’s strength between the fully-differential input. Thus, the mismatch effect is efficiently relieved in terms of area and power consumption. The proposed calibration restores the SNR by 19.54 dB even under the worst self-capacitance mismatch case.