This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6-8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics.

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This paper presents an offset calibration approach that exploits the dynamic characteristics of a comparator to achieve a wide linear tuning range by placing varactors at two different internal nodes: the drains of the input pairs ( nodes) for high linearity, and the output nodes for wider compensation range. The comparators are placed in a 3-bit 1GS/s flash ADC that will be integrated into an 8-bit hybrid ADC architecture. A digital calibration scheme controls the gate voltages of the varactors and detects the minimum offset condition. The proposed configuration was simulated with a transistor-level flash ADC design in 0.13µm CMOS technology and a Verilog-A behavioral implementation of the calibration circuitry. The ADC consumes 1.48mW of power (excluding the calibration circuitry, flip-flops and encoder) from a 1.2V voltage supply. Monte Carlo simulation results indicate that the method reduces the 3-sigma input offset of the comparator from 36.9mV to 1.6mV. The simulated effective number of bits (ENOB) of the flash ADC is 2.96 bits.