Multi-view applications provide viewers a whole new viewing experience and multi-view video coding (MVC) that plays a key role in distributing multi-view video contents through networks with limited bandwidth. The main objective of Multi-View video compression is to increase the compression ratio with minimum loss. The Hierarchical B picture (HBP) prediction structure is very helpful in multi-view video coding due to a reduction in the computational complexity in MVC and improves the coding efficiency. In this paper, Low Cost Multi-view Video Coding Discrete Wavelet Transform (LC-MVC-DWT) is introduced to improve the Peak-Signal-to-Noise-Ratio (PSNR) value, Application Specified Integrated Chip (ASIC) performances and Field Programmable Gate array (FPGA) performances. FPGA results showed that LUT, slices, flip flops, frequency improved and also ASIC results showed that area, power, delay, Area Power Product (APP) and Area Delay Product (ADP) improved in the LC-MVC-DWT technique compared to the existing methods.

The video is one of the most useful and most appealing medium to represent some information. More usage of digital multi-media via communications media, wireless communications, intranet, internet and cellular mobile leads to the uncontrollable growth of data in media. The video compression technique is used in this research work to improve the processing speed of the entire system. In this work, Low Cost - Multi Video Coding - Hybrid Compression and Decompression (LC-MVC-HCD) method is used to reduce computation complexity. The combinational of Discrete Wavelet Transform (DWT) and Discrete Cosine Transform (DCT) algorithms are denoted as hybrid algorithm. Based on this hybrid algorithm, the compression process is performing which improves the video coding efficiency of MVC. The LC-MVC-HCD methodwas implemented in the Matlab, Xilinx and Cadence tool. In Application Specific Integrated Circuit (ASIC) implementation, the area, power, and delay minimized by using the cadence encounter tool with 180nm and 45nm technology. In Field Programmable Gate Array (FPGA) implementation, the number of Lookup Tables (LUTs), slice, and flip-flop are minimized based on two different kinds of Virtex devices such as Virtex -6 and Virtex-7. In Matlab, Peak Signal to Noise Ratio (PSNR), computational time and bit error rate were analyzed for the LC-MVC-HCD method. The experimental outcome showed that the proposed methodology has improved performance ASIC and FPGA up to 2-3% compared to existing methods like Direct mode decision MVC and LC-MVC-DWT.