Deep learning is a branch of machine learning that tries to model high-level abstractions of data using multiple layers of neurons consisting of complex structures or non-liner transformations. With the increase of the amount of data and the power of computation, neural networks with more complex structures have attracted widespread attention and been applied to various fields. This paper provides an overview of deep learning in neural networks including popular architecture models and training algorithms.

High efficient implementation of scaling in residue number system (RNS) is one of the critical issues for the applications of RNS in digital signal processing (DSP) systems. In this paper, an efficient scaling algorithm for signed integers in RNS is proposed firstly through introducing a correction constant in negative integers scaling procedure. Based on the proposed scaling algorithm, an efficient RNS 2 n scaling implementation method is presented, in which Chinese remainder theorem (CRT) and a redundant modulus are used to perform the base extension to obtain the least significant n bits of RNS integers. With the redundant modulus, the RNS sign detection can be achieved by the parity detection. And then, an approach to update the residue digit of the redundant channel is also proposed. Meanwhile, this paper provides a method of computing the correction constant of the redundant channel in negative integers scaling. The analysis results indicate that the complexity of the proposed scaling algorithm grows linearly with the word-length of the RNS dynamic range without using Look-up Table (LUT). Furthermore, the proposed algorithm is employed for a specific moduli set 2 n scaling. The synthesis results show that the critical path of the proposed algorithm is shortened by 12%, the area and power consumption performance is improved by about 35%, compared to the existing cascading 2 n scaling method for very large scale integration (VLSI) implementation under the same restriction. Besides, the VLSI layout indicates that the parallel structure is simpler. CitationMa S, Hu J H, Ye Y L, et al. A 2 n scaling scheme for signed RNS integers and its VLSI implementation.

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In order to improve the image encryption system's ability to resist plaintext, noise, and data loss attacks, in this paper, a new plaintext-related and chaos-based image encryption scheme is proposed, which includes two rounds of encryption operations. The block parity checking, performed in the first round of encryption, is used to associate the plaintext information with a secret key so that the encryption scheme can resist plaintext attacks. Moreover, repetitive coding, which is adopted in the second round of encryption, is used to protect the plaintext-related parameters against noise and data loss attacks. Meanwhile, a highspeed digital chaotic sequence generator based on permutation polynomials and residue number system is also presented. The detailed performance evaluations, including key space, key sensitivity, differential attack resisting ability, anti-noise ability, correlation coefficient, and information entropy, show that our scheme not only possesses the properties of good randomness and large key space but also has a high degree of robustness against plaintext, noise, and data loss attacks.

Residue number system (RNS) has received considerable attention since decades before, because it has inherent carry-free and parallel properties in addition, subtraction, and multiplication operations. For an odd moduli set, the fundamental problems in RNS, such as number comparison, sign determination, and overflow detection, can be solved based on parity checking. The paper proposes a parity checking algorithm along with related propositions and the certification based on the celebrated Chinese remainder theory (CRT) and mixed radix conversion (MRC) for the moduli set {2 n −1, 2 n +1, 2 2n +1}. The parity checker consists of two modular adders and a carry-look-ahead chain. The hardware implementation requires less area and path delay. Besides, the implementations of number comparison, sign determination, and overflow detection, which are based on this parity checker, are also performed in this paper. And this kind of parity checker can be used as a basic element to design ALUs and DSP module in RNS.