A new method is proposed to extract the energy distribution of negative charges, which results from electron trapping by traps in the gate stack of nMOSFET during positive bias temperature instability (PBTI) stress based on the recovery measurement. In our case, the extracted energy distribution of negative charges shows an obvious dependence on energy, and the energy level of the largest energy density of negative charges is 0.01 eV above the conduction band of silicon. The charge energy distribution below that energy level shows strong dependence on the stress voltage.

Encryption is an important step for secure data transmission, and a true random number generator (TRNG) is a key building block in many encryption algorithms. Static random-access memory (SRAM) chips can be easily available sources of true random numbers, benefiting from noisy SRAM cells whose start-up values flip between different power-on cycles. Embarking from this phenomenon, a novel performance (i.e., randomness and throughput) improvement method of SRAM-based TRNG is proposed, and its implementation can be divided into two phases: irradiation exposure and hardware postprocessing. As the randomness of original SRAM power-on values is fairly low, ionization irradiation is utilized to enhance its randomness, and the min-entropy can increase from about 0.03 to above 0.7 in the total ionizing irradiation (TID) experiments. Additionally, while the data remanence effect hampers obtaining random bitstreams with high speed, the ionization irradiation can also weaken this impact and improve the throughput of TRNG. In the hardware postprocessing stage, Secure Hash Algorithm 256 (SHA-256) is implemented on a Field Programmable Gate Array (FPGA) with clock frequency of 200 MHz. It can generate National Institute of Standards and Technology (NIST) SP 800-22 compatible true random bitstreams with throughput of 178 Mbps utilizing SRAM chip with 1 Mbit memory capacity. Furthermore, according to different application scenarios, the throughput can be widely scalable by adjusting clock frequency and SRAM memory capacity, which makes the novel TRNG design applicable for various Internet of Things (IOT) devices.

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