The coordinate rotation digital computer (CORDIC) is a class of shift-add algorithms for rotating vectors in plane. Several techniques use the trigonometry function to compute the digital waves, but that requires expensive memory usage. Due to the flexible characteristics, CORDIC is best alternative and allows high quantization accuracy by maximum word length. The linear-rate convergence creates the major problem in CORDIC algorithm with the source of word-length and iteration speed. The power consumption also a major issue here to affects the performance by array of shift-add operations. For further enhancement, in this paper, we propose a low power and high speed CORDIC (LH-CORDIC) design with an improved power control and hardware reduction techniques. We employ the canonical signed-digit (CSD) technique and Hcub algorithm for reducing the number of shifters and adder/subtractor in the design. Then, we propose an adder based on the advanced Boolean logic technique. These three techniques are used to redesign the entire CORDIC logic stages thereby contributing in power consumption reduction. The functionality of proposed LH-CORDIC algorithm is assessed through FPGA implementations. The simulation result shows that the proposed method has higher frequency of 78.91%, 83.42%, 79.89% and 77.01% when compared with conventional CORDIC method.

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