Optical microlithography is the technique of printing a set of shapes on a wafer using light transmitted through a template called a mask. Repeatedly printing and stacking such shapes on top of each other to build electrical circuits allows us to manufacture chips in high volume. However this technique has now reached its fundamental physical limits of resolution. Current 193nm wavelength light is no longer sufficient to reliably transfer patterns which are now in the sub-100nm dimensional range. This has led to increased research in optimizing lithographic masks to pre-compensate for distortions introduced by the lithographic process. This is called mask optimization. In this contest, students are provided with a sample lithographic model which simulates the transfer of a mask pattern on to wafer. The mask is assumed to be a pixelated template, where every pixel can be turned on or off, to indicate where light passes through, or is blocked. Contestants are also provided with models to predict the robustness of their pattern i.e. how much variability is in the transferred pattern. Given these tools, the objective is to minimize the variability in the wafer image, as measured by process variability (PV) bands. This is subject to the constraints of runtime and satisfying pattern fidelity i.e. the transferred pattern should resemble the target pattern. Benchmarks are provided in the form of collections of geometric shapes, each of which provides a challenge in printing at sub-wavelength.

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Existing optical proximity correction tools aim at minimizing edge placement errors (EPE) due to the optical and resist process by moving mask edges. However, in low-k1 lithography, especially at 45nm and beyond, printing perfect polygons is practically impossible to achieve in addition to incurring prohibitively high mask complexity and cost. Given the impossibility of perfect printing, we argue that aiming to reduce the error of electrical discrepancy between the ideal and the printed contours is a more reasonable strategy. In fact, we show that contours with non-minimal EPE may result in closer match to the desired electrical performance.Towards achieving this objective, we developed a new electrically driven OPC (ED-OPC) algorithm. The tool combines lithography simulation with an accurate contour-based model of shape electrical behavior to predict the on/off current through a transistor gate. The algorithm then guides edge movements to minimize the error in current, rather than in edge placement, between current values for printed and target shapes. The results on industrial 45nm SOI layouts using high-NA immersion lithography models show up to a 5% improvement in accuracy of timing over conventional OPC, while at the same time showing up to 50% reduction in mask complexity for gate regions. The results confirm that better timing accuracy can be achieved despite larger edge placement error.

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